EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 140

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Data Transfer Procedure with SPI Configured as a Slave
SPI Registers
6. When the SPI data transfer is complete, de-assert the ENABLE pin of the slave
Follow the steps below for data transfer with SPI configured as the slave:
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI
3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.
There are six registers in the Serial Peripheral Interface which provide control, status, and
data storage functions. The SPI registers are described in the following section.
SPI Baud Rate Generator Registers—Low Byte and High Byte
These registers hold the Low and High bytes of the 16-bit divisor count loaded by the
processor for baud rate generation. The 16-bit clock divisor value is returned by
{SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to
0002h
and
between
A Write to either the Low or High byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and the count restarted. See
Table
Table 69. SPI Baud Rate Generator Register—Low Byte (SPI_BRG_L = 00B8h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_L
device.
slave is currently receiving data.
FFFFh
70.
. When configured as a Master, the 16-bit divisor value must be between
0004h
, inclusive. When configured as a Slave, the 16-bit divisor value must be
and
00h–FFh
Value
FFFFh
R/W
, inclusive.
7
0
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
Serial Peripheral Interface
R/W
Table 69
2
0
eZ80L92 MCU
R/W
1
1
and
0003h
R/W
0
0
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