EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 17

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
PS013014-0107
Pin No
43
44
45
46
47
48
49
50
51
IORQ
MREQ
RD
WR
INSTRD
WAIT
RESET
Symbol
V
V
DD
SS
Function
Power Supply
Ground
Input/Output
Request
Memory
Request
Read
Write
Instruction
Read Indicator
WAIT Request Input, Active Low
Reset
Signal Direction
Bidirectional, Active
Low
Bidirectional, Active
Low
Output, Active Low
Output, Active Low
Output, Active Low
Schmitt Trigger Input,
Active Low
Power Supply.
Ground.
IORQ indicates that the CPU is accessing
a location in I/O space. RD and WR
indicate the type of access. The eZ80L92
MCU does not drive this line during
RESET. It is an input in bus acknowledge
cycles.
MREQ Low indicates that the CPU is
accessing a location in memory. The RD,
WR, and INSTRD signals indicate the
type of access. The eZ80L92 MCU does
not drive this line during RESET. It is an
input in bus acknowledge cycles.
RD Low indicates that the eZ80L92 MCU
is reading from the current address
location. This pin is tristated during bus
acknowledge cycles.
WR indicates that the CPU is writing to the
current address location. This pin is
tristated during bus acknowledge cycles.
INSTRD (with MREQ and RD) indicates
the eZ80L92 MCU is fetching an
instruction from memory. This pin is
tristated during bus acknowledge cycles.
to wait additional clock cycles for an
external peripheral or external memory to
complete its Read or Write operation.
This signal is used to initialize the
eZ80L92 MCU. This input must be Low for
a minimum of 3 system clock cycles, and
must be held Low until the clock is stable.
This input includes a Schmitt trigger to
allow RC rise times.
Description
Driving the WAIT pin Low forces the CPU
Product Specification
Architectural Overview
11