EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 171

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

eZ80L92 MCU
Product Specification
165
ZDI Block Write
The Block Write operation is initiated in the same manner as the single-byte Write opera-
tion, but instead of terminating the Write operation after the first data byte is transferred,
the ZDI master can continue to transmit additional bytes of data to the ZDI slave on the
eZ80L92. After the receipt of each byte of data the ZDI register address increments by 1.
If the ZDI register address reaches the end of the Write-Only ZDI register address space
(
), the address stops incrementing.
Figure 41
illustrates the timing for ZDI Block
30h
Write operations.
ZDI Data Bytes
ZCL
7
8
9
1
2
3
7
8
9
1
2
9
ZDA
A0
Write
0/1
D7
D6
D5
D1
D0
0/1
D7
D6
1
msb
lsb
msb
of DATA
of DATA
of DATA
Byte 1
Byte 1
Byte 2
lsb of
Single-Bit
Single-Bit
ZDI Address
Byte Separator
Byte Separator
Figure 41. ZDI Block Data Write Timing
ZDI Read Operations
ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write opera-
tions, with the exception that the R/W bit of the ZDI register address is set to 1. Upon
receipt of a slave address with the R/W bit set to 1, the eZ80L92’s ZDI block loads the
selected data into the shifter at the beginning of the first cycle following the single-bit data
separator. The most significant bit (msb) is shifted out first.
Figure 42
illustrates the timing
for ZDI single-byte Read operations.
PS013014-0107
ZiLOG Debug Interface