EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 172

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
ZDA
ZCL
ZDA
ZCL
Operation of the eZ80L92 During ZDI Break Points
ZDI Address
ZDI Address
lsb of
lsb of
A0
7
A0
7
ZDI Block Read
A Block Read operation is initiated the same as a single-byte Read; however, the ZDI
master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to
output data. The ZDI register address counter increments with each Read. If the ZDI
register address reaches the end of the Read-Only ZDI register address space (
address stops incrementing.
If the ZDI forces the CPU to break, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that can operate auton-
omously from the CPU may continue to operate, if so enabled. For example, the Watchdog
Timer and Programmable Reload Timers continue to count during a ZDI break point.
Read
Read
8
8
Byte Separator
Byte Separator
Single-Bit
Single-Bit
0/1
0/1
Figure 42. ZDI Single-Byte Data Read Timing
9
9
Figure 43. ZDI Block Data Read Timing
of DATA
of DATA
Byte 1
msb
msb
D7
D7
1
1
D6
D6
2
Figure 43
2
D5
3
D5
3
illustrates the ZDI’s Block Read timing.
ZDI Data Byte
D4
ZDI Data Bytes
4
D1
7
of DATA
D3
Byte 1
5
D0
lsb
8
Byte Separator
Single-Bit
D2
6
0/1
9
D1
of DATA
Product Specification
7
Byte 2
msb
D7
1
of DATA
ZiLOG Debug Interface
D0
lsb
8
START Signal
eZ80L92 MCU
D6
End of Data
2
or New ZDI
1
20h
9
1
), the
9
166

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