EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 176

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Table 92. ZDI Address Match Registers ZDI_ADDR0_L = 00h, ZDI_ADDR0_H
= 01h, ZDI_ADDR0_U = 02h, ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h,
ZDI_ADDR1_U = 06h, ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h,
ZDI_ADDR2_U = 0Ah, ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, and
ZDI_ADDR3_U = 0Eh in the ZDI Register Write-Only Address Space
ZDI Break Control Register
The ZDI Break Control register is used to enable break points. ZDI asserts a BREAK
when the CPU instruction address, ADDR[23:0], matches the value in the ZDI Address
Match 3 registers, {ZDI_ADDR3_U, ZDI_ADDR3_H, ZDI_ADDR3_L}. Breaks only
occur on an instruction boundary. If the instruction address is not the beginning of an
instruction (that is, for multibyte instructions), then the BREAK occurs at the end of the
current instruction. The BRK_NEXT bit is set to 1. The BRK_NEXT bit must be reset to 0
to release the BREAK. See
Table 93. ZDI Break Control Register (ZDI_BRK_CTL = 10h in the ZDI Write-
Only Register Address Space)
Bit
Reset
CPU Access
Note: W = Write-only.
Bit
Position
[7:0]
ZDI_ADDRx_L,
ZDI_ADDRx_H,
or
ZDI_ADDRx_U
Bit
Reset
CPU Access
Note: W = Write-only.
00h–FFh The four sets of ZDI address match registers are used
Value
W
W
Table
X
7
7
0
Description
for setting the addresses for generating break points.
The 24-bit addresses are supplied by {ZDI_ADDRx_U,
ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
93.
W
W
X
6
6
0
W
W
X
5
5
0
W
W
X
4
4
0
W
W
X
3
3
0
Product Specification
W
W
X
2
2
0
ZiLOG Debug Interface
eZ80L92 MCU
W
W
X
1
1
0
W
W
X
0
0
0
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