EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 177

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
Bit
Position
7
BRK_NEXT
6
brk_addr3
5
brk_addr2
4
brk_addr1
3
brk_addr0
2
ign_low_1
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
The ZDI BREAK on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
The ZDI BREAK on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. break points only occur on the first Op Code in a
multibyte Op Code instruction. If the ZCL pin is High and
the ZDA pin is Low at the end of RESET, this bit is set to 1
and a BREAK occurs on the first instruction following the
RESET. This bit is set automatically during ZDI BREAK on
address match. A BREAK can also be forced by writing a 1
to this bit.
The ZDI BREAK, upon matching break address 3,
is disabled.
The ZDI BREAK, upon matching break address 3,
is enabled.
The ZDI BREAK, upon matching break address 2,
is disabled.
The ZDI BREAK, upon matching break address 2,
is enabled.
The ZDI BREAK, upon matching break address 1,
is disabled.
The ZDI BREAK, upon matching break address 1,
is enabled.
The ZDI BREAK, upon matching break address 0,
is disabled.
The ZDI BREAK, upon matching break address 0,
is enabled.
The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If BRK_ADDR1 is set to 1, ZDI
initiates a BREAK when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H, ZDI_ADDR1_L}.
The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If BRK_ADDR1 is set to 1, ZDI
initiates a BREAK when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2-byte value
{ZDI_ADDR1_U, ZDI_ADDR1_H}. As a result, a BREAK
can occur anywhere within a 256-byte page.
Product Specification
ZiLOG Debug Interface
eZ80L92 MCU
171

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