EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 181

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Table 96. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in
the ZDI Register Write-Only Address Space)
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register must be written during ZDI Debug mode (that is, following
a BREAK). See
Table 97. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register
Write-Only Address Space)
Hex
Value
09
0A
0B
Note: The
Bit
Reset
CPU Access
Note: W = Write-only.
The ZDI programmer must execute the exchange instruction (EXX) to gain access to the
alternate
eZ80 CPU
Command
Reset ADL
ADL
Exchange CPU register sets
AF
BC
DE
HL
Read memory from current PC
value, increment PC
eZ80 CPU
Table
←
←
←
←
←
AF’
HL’
BC’
DE’
’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly.
0
97.
register set.
W
7
0
W
6
0
W
5
0
Hex
Value
89
8A
8B
W
(Continued)
4
0
Command
Reserved
Reserved
Write memory from current PC
value, increment PC
W
3
0
Product Specification
W
2
0
ZiLOG Debug Interface
eZ80L92 MCU
W
1
0
W
0
0
175