EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 190

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Table 107. OCI Pins
PS013014-0107
Symbol
TCK
TMS
TDI
TDO
TRIGOUT
OCI Interface
Name
Clock.
Test Mode Select
Data In
Data Out
Trigger Output
There are five dedicated pins on the eZ80L92 MCU for the OCI interface. Four pins
(TCK, TMS, TDI, and TDO) are required for IEEE Standard 1149.1-compatible JTAG
ports. The TRIGOUT pin provides additional testability features.
OCI pins
.
Type
Input
Input
Input
(OCI enabled)
I/O
(OCI disabled)
Output
Output
Description
Asynchronous to the primary eZ80L92 system clock.
The TCK period but must be at least twice the system
clock period. During RESET, this pin is sampled to
select either OCI or ZDI DEBUG modes. If Low
during RESET, the OCI is enabled. If High during
RESET, the OCI is powered down and ZDI DEBUG
mode is enabled. When ZDI DEBUG mode is active,
this pin is the ZDI clock. On-chip pull-up ensures a
default value of 1 (High).
This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
Serial test data input. On-chip pull-up ensures a
default value of 1 (High). This pin is input-only when
the OCI is enabled. The input data is sampled on the
rising edge of the TCK signal.
When the OCI is disabled, this pin functions as the
ZDA (ZDI Data) I/O pin.
The output data changes on the falling edge of the
TCK signal.
Generates an active High trigger pulse when valid
OCI trigger events occur. Output is tristate when no
data is being driven out.
Product Specification
Table 107
On-Chip Instrumentation
eZ80L92 MCU
lists these five
184