EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 63

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Intel Bus Mode (Separate Address and Data Buses)
During Read operations with separate address and data buses, the Intel Bus Mode employs
4 states (T1, T2, T3, and T4) as described in
Table 16. Intel
STATE T1
STATE T2
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
The Read cycle begins in State T1. The CPU drives the address onto the
address bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
During State T2, the CPU asserts the RD signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
RD
®
Figure 9. Intel
Bus Mode Read States (Separate Address and Data Buses)
®
Multiplexed
Bus Mode
Controller
Controller
Bus Mode Signal and Pin Mapping
Bus
ADDR[7:0]
Table
16.
Intel Bus
Signal Equvalents
ALE
RD
WR
READY
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Chip Selects and Wait States
Product Specification
eZ80L92 MCU
57