EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 70

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

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Table 20. Motorola Bus Mode Read States
PS013014-0107
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
During state S3, no bus signals are altered.
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
During state S5, no bus signals are altered.
On the rising edge of state S2, the CPU asserts AS and DS.
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each WAIT state is a full bus mode cycle.
During Write operations, the Motorola Bus Mode employs 8 states (S0, S1, S2, S3, S4, S5,
S6, and S7) as described in
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
Figure 14. Motorola Bus Mode Signal and Pin Mapping
Table
Bus Mode
Controller
20.
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
WAIT
) states until DTACK is
Chip Selects and Wait States
Product Specification
eZ80L92 MCU
64

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