EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 73

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Chip Select Registers
System Clock
ADDR[23:0]
DATA[7:0]
or IORQ
DTACK
MREQ
Switching Between Bus Modes
Each time the bus mode controller must switch from one bus mode to another, there is a
one-cycle eZ80 system clock delay. An extra clock cycle is not required for repeated
accesses in any of the bus modes; nor is it required when the eZ80L92 switches to eZ80
Bus Mode. The extra clock cycles are not shown in the timing examples. Due to the asyn-
chronous nature of these bus protocols, the extra delay does not impact peripheral commu-
nication.
Chip Select x Lower Bound Registers
For Memory Chip Selects, the Chip Select x Lower Bound register (see
the lower bound of the address range for which the corresponding Memory Chip Select (if
CSx
R/W
DS
AS
Figure 16. Motorola Bus Mode Write Timing Example
S0
S1
S2
S3
S4
S5
S6
Chip Selects and Wait States
Product Specification
S7
Table
eZ80L92 MCU
22) defines
67