EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 75

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Chip Select x Upper Bound Registers
For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in
defines the upper bound of the address range for which the corresponding Chip Select (if
enabled) can be active. For I/O Chip Selects, this register produces no effect. The reset
state for the Chip Select 0 Upper Bound register is
Chip Select upper bound registers is
Table 23. Chip Select x Upper Bound Registers (CS0_UBR = 00A9h,
Bit
CS0_UBR Reset
CS1_UBR Reset
CS2_UBR Reset
CS3_UBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSx_UBR
CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h)
00h–FFh
Value
R/W
7
1
0
0
0
Description
For Memory Chip Selects (CSx_IO = 0)
This byte specifies the upper bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in
these registers for determining whether a Chip Select
signal should be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.
R/W
6
1
0
0
0
00h
.
R/W
5
1
0
0
0
FFh
R/W
4
1
0
0
0
, while the reset state for the other
R/W
3
1
0
0
0
Chip Selects and Wait States
Product Specification
R/W
2
1
0
0
0
eZ80L92 MCU
R/W
1
1
0
0
0
Table
R/W
0
1
0
0
0
23,
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