MPC852TVR50A Freescale Semiconductor, MPC852TVR50A Datasheet - Page 13

• Manufacturer Part Number: MPC852TVR50A
• Description: IC MPU POWERQUICC 50MHZ 256PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC852TVR50A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC852TADS-KIT
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• I/o Voltage: 3.3 V
• Interface Type: SPI, UART
• Minimum Operating Temperature: 0 C
• Program Memory Size: 4 KB
• Program Memory Type: EPROM/Flash
• Core Size: 32 Bit
• Cpu Speed: 50MHz
• Embedded Interface Type: SPI
• Digital Ic Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured
with the mandatory value in
11 Layout Practices
Each V
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V
0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board designed
should be characterized and additional appropriate decoupling capacitors should be used if required. The
capacitor leads and associated printed-circuit traces connecting to chip V
less than half an inch per capacitor lead. At a minimum, a four-layer board employing two inner layers as
V
All output pins on the MPC852T have fast rise and fall times. Printed-circuit (PC) trace interconnection
length should be minimized to minimize undershoot and reflections that these fast output switching times
cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths
of six inches are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads, because these loads create higher transient
currents in the V
Special care should be taken to minimize the noise levels on the PLL supply pins. For more information,
please refer to the MPC866 PowerQUICC™ Family Reference Manual, Section 14.4.3, “Clock
Synthesizer Power (V
Freescale Semiconductor
DD
and GND planes should be used.
DD
pin on the MPC852T should be provided with a low-impedance path to the board’s supply. Each
HRCW (Hardware reset configuration word)
SIUMCR (SIU module configuration register)
MBMR (Machine B mode register)
PAPAR (Port A pin assignment register)
PADIR (Port A data direction register)
PBPAR (Port B pin assignment register)
PBDIR (Port B data direction register)
PCPAR (Port C pin assignment register)
PCDIR (Port C data direction register)
DD
and GND circuits. Pull up all unused inputs or signals that are inputs during reset.
DDSYN
Register/Configuration
Table 6. Mandatory Reset Configuration of MPC852T
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Table 6
, V
SSSYN
in the boot code after the reset deasserts.
, V
DD
SSSYN1
power supply should be bypassed to ground using at least four
).”
HRCW[DBGC]
SIUMCR[DBGC]
PAPAR[4–7]
MBMR[GPLB4DIS}
PAPAR[12–15]
PADIR[4–7]
PADIR[12–15]
PBPAR[14]
PBPAR[16–23]
PBPAR[26–27]
PBDIR[14]
PBDIR[16–23]
PBDIR[26–27]
PCPAR[8–11]
PCDIR[14]
PCDIR[8–11]
PCDIR[14]
Field
DD
and GND should be kept to
(Binary)
Value
X1
X1
0
0
1
0
1
0
1
Layout Practices
13