MPC852TVR50A Freescale Semiconductor, MPC852TVR50A Datasheet - Page 16

IC MPU POWERQUICC 50MHZ 256PBGA

MPC852TVR50A

Manufacturer Part Number
MPC852TVR50A
Description
IC MPU POWERQUICC 50MHZ 256PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC Ir
Datasheet

Specifications of MPC852TVR50A

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Development Tools By Supplier
MPC852TADS-KIT
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
8 KB
I/o Voltage
3.3 V
Interface Type
SPI, UART
Minimum Operating Temperature
0 C
Program Memory Size
4 KB
Program Memory Type
EPROM/Flash
Core Size
32 Bit
Cpu Speed
50MHz
Embedded Interface Type
SPI
Digital Ic Case Style
BGA
No. Of Pins
256
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Bus Signal Timing
16
B16a
B16b
B17a
B22a
B22b
Num
B22c
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
CLKOUT to TEA High-Z
(MIN = 0.00 × B1 + 2.50)
TA, BI valid to CLKOUT (setup time)
(MIN = 0.00 × B1 + 6.00)
TEA, KR, RETRY, CR valid to CLKOUT
(setup time) (MIN = 0.00 × B1 + 4.5)
BB, BG, BR, valid to CLKOUT (setup time)
3
CLKOUT to TA, TEA, BI, BB, BG, BR valid
(hold time) (MIN = 0.00 × B1 + 1.00
CLKOUT to KR, RETRY, CR valid (hold
time) (MIN = 0.00 × B1 + 2.00)
D(0:31), DP(0:3) valid to CLKOUT rising
edge (setup time)
(MIN = 0.00 × B1 + 6.00)
CLKOUT rising edge to D(0:31), DP(0:3)
valid (hold time)
D(0:31), DP(0:3) valid to CLKOUT falling
edge (setup time)
(MIN = 0.00 × B1 + 4.00)
CLKOUT falling edge to D(0:31), DP(0:3)
valid (hold Time)
CLKOUT rising edge to CS asserted
GPCM ACS = 00 (MAX = 0.25 × B1 + 6.3)
CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
(MAX = 0.00 × B1 + 8.00)
CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 × B1 + 6.3)
CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
CLKOUT rising edge to CS negated
GPCM read access, GPCM write access
ACS = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 × B1 + 8.00)
A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)
(4MIN = 0.00 × B1 +.000)
Characteristic
5
7
(MIN = 0.00 × B1 + 1.00
5
7
(MIN = 0.00 × B1 + 2.00)
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Table 9. Bus Operation Timings (continued)
4
)
6
)
10.90
2.50
6.00
4.50
4.00
1.00
2.00
6.00
1.00
4.00
2.00
7.60
7.60
2.00
5.60
Min
33 MHz
15.00
13.80
13.80
18.00
Max
8.00
8.00
10.90
2.50
6.00
4.50
4.00
1.00
2.00
6.00
1.00
4.00
2.00
6.30
6.30
2.00
4.30
Min
40 MHz
15.00
12.50
12.50
16.00
Max
8.00
8.00
2.50
6.00
4.50
4.00
1.00
2.00
6.00
1.00
4.00
2.00
5.00
5.00
7.00
2.00
3.00
Min
50 MHz
15.00
11.30
11.30
14.10
Max
8.00
8.00
Freescale Semiconductor
2.50
6.00
4.50
4.00
2.00
3.80
3.80
5.20
2.00
6.00
2.00
4.00
2.00
2.00
1.80
Min
66 MHz
15.00
10.00
10.00
12.30
Max
8.00
8.00
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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