MPC852TVR50A Freescale Semiconductor, MPC852TVR50A Datasheet - Page 2

• Manufacturer Part Number: MPC852TVR50A
• Description: IC MPU POWERQUICC 50MHZ 256PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC852TVR50A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC852TADS-KIT
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• I/o Voltage: 3.3 V
• Interface Type: SPI, UART
• Minimum Operating Temperature: 0 C
• Program Memory Size: 4 KB
• Program Memory Type: EPROM/Flash
• Core Size: 32 Bit
• Cpu Speed: 50MHz
• Embedded Interface Type: SPI
• Digital Ic Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
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The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICC™ family, and can operate up to
100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V
I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a
versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of
controller applications. It particularly excels in Ethernet control applications, including CPE equipment,
Ethernet routers and hubs, VoIP clients, and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit
microprocessor that implements the PowerPC architecture, incorporating memory management units
(MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.
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The MPC852T is comprised of three modules that each use a 32-bit internal bus: an MPC8xx core, system
integration unit (SIU), and communication processor module (CPM).
The following list summarizes the key MPC852T features:
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Overview
Features
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— 50/66 MHz core frequencies support both 1:1 and 2:1 modes
— 80/100 MHz core frequencies support 2:1 mode only
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
– 4-Kbyte instruction caches is two-way, set-associative with 128 sets
– 4-Kbyte data cachesis two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
– Caches are physically addressed, implement a least recently used (LRU) replacement
spaces, and 16 protection groups
cache blocks
algorithm, and are lockable on a cache block basis
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor