EZ80L92AZ050SC00TR Zilog, EZ80L92AZ050SC00TR Datasheet - Page 77
EZ80L92AZ050SC00TR
Manufacturer Part Number
EZ80L92AZ050SC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ050SC00T
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PS013014-0107
Chip Select x Bus Mode Control Registers
The Chip Select Bus Mode register, detailed in
eZ80, Z80, Intel
to interface to peripherals based on the Z80, Intel
interfaces. When a bus mode other than eZ80 is programmed for a particular Chip Select,
the CSx_WAIT setting in that Chip Select Control Register is ignored.
Table 25. Chip Select x Bus Mode Control Registers (CS0_BMC = 00F0h,
Bit
CS0_BMC Reset
CS1_BMC Reset
CS2_BMC Reset
CS3_BMC Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:6]
BUS_MODE
5
AD_MUX
4
CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)
®
, or Motorola Bus Modes. Changing the bus mode allows the eZ80L92
Value
00
01
10
11
0
1
0
R/W
7
0
0
0
0
Description
eZ80 bus mode.
Z80 bus mode.
Intel
Motorola bus mode.
Separate address and data.
Multiplexed address and data—appears on data bus
DATA[7:0].
Reserved.
®
R/W
6
0
0
0
0
bus mode.
R/W
5
0
0
0
0
Table
®
-, or Motorola-style asynchronous bus
R
4
0
0
0
0
25, configures the Chip Select for
R/W
3
0
0
0
0
Chip Selects and Wait States
Product Specification
R/W
2
0
0
0
0
eZ80L92 MCU
R/W
1
1
1
1
1
R/W
0
0
0
0
0
71
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