Z8L18020VSC Zilog, Z8L18020VSC Datasheet - Page 62
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Z8L18020VSC
Manufacturer Part Number
Z8L18020VSC
Description
IC 20MHZ LOW PWR S180 68-PLCC
Manufacturer
Zilog
Datasheet
1.Z8S18010PSG.pdf
(71 pages)
Specifications of Z8L18020VSC
Processor Type
Z80
Features
Enhanced DMA Support
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8L18020VSC
Manufacturer:
NXP
Quantity:
1 302
first opcode should be interpreted as the stacked
Read-Only.
Bits
as bits
rupts for the
This register is used in handling
able or disable Maskable Interrupt Level
and
code is fetched.
by writing it with a ; however,
1
terrupt occurs, the contents of
dress of the undefined instruction to be determined. This in-
terrupt is necessary because the
the second or third byte of the opcode.
stacked PC value to be correctly adjusted. If
and
under program control.
1
of the Interrupt Vector Low Register ( ) are used
, the first opcode address is stacked
pins.
enable and disable the external interrupt inputs
of the synthesized interrupt vector during inter-
This bit is set to
and
can be reset under program control
pins and for the DMAs, ASCIs,
is reset to
1
when an undefined op-
cannot be written with
allow the starting ad-
interrupts and to en-
may occur on either
When a
0
during
and the
allows the
.
0
, the
. If
in-
is
.
PRTs, and CSI/O. These three bits are cleared to
terrupts from:
A
a
and
sequence when an undefined opcode fetch occurs. This fea-
ture can be used to increase software reliability, implement
an
opcode fetch cycles and also if an undefined opcode is
fetched during the interrupt acknowledge cycle for
when Mode
When a
1. Sets the
2. Saves the current Program Counter (PC) value,
3. Resumes execution at logical address
0
1
extended
register to
disables it. A
reflecting the location of the undefined opcode, on the
stack.
in a bit enables the corresponding interrupt level while
and
If logical address 0000H is mapped to physical address
00000H, the vector is the same as for
case, testing the
start at physical address 00000H was caused by
or
(Figure 74).
to
instruction set, or both.
0
.
, respectively.
is used.
sequence occurs, the Z8S180/Z8L180:
1
.
.
The Z8S180/Z8L180 generates a
• Bidirectional Centronics controller
• External interrupt input
bit in the Interrupt
sets
bit in
enables and disables in-
to
reveals whether the re-
1
may occur during
0
and clears
.
/Control (
0
. In this
ZiLOG
during
)