EZ80L92AZ050EC00TR Zilog, EZ80L92AZ050EC00TR Datasheet - Page 145
EZ80L92AZ050EC00TR
Manufacturer Part Number
EZ80L92AZ050EC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ050EC00T
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I
PS013014-0107
2
C Serial I/O Interface
General Characteristics
The I
modes:
•
•
•
•
The I
and SCL are bidirectional lines, connected to a positive supply voltage via an external
pull-up resistor. When the bus is free, both lines are High. The output stages of devices
connected to the bus must be configured as open-drain outputs. Data on the I
transferred at a rate of up to 100 Kbps in STANDARD mode, or up to 400 Kbps in FAST
mode. One clock pulse is generated for each data bit transferred.
Clocking Overview
If another device on the I
the I
determined by the device that generates the shortest High clock period. The Low period of
the clock is determined by the device that generates the longest Low clock period.
A slave may stretch the Low period of the clock to slow down the bus master. The Low
period may also be stretched for handshaking purposes. This can be done after each bit
transfer or each byte transfer. The I
IFLG bit in the I2C_CTL register is cleared.
Bus Arbitration Overview
In MASTER mode, the I
a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not-Acknowledge
bit, the I
address, the I
the general call address.
MASTER TRANSMIT
MASTER RECEIVE
SLAVE TRANSMIT
SLAVE RECEIVE
2
2
2
C synchronizes its clock to the I
C interface consists of the Serial Clock (SCL) and the Serial Data (SDA). Both SDA
C serial I/O bus is a two-wire communication interface that can operate in four
2
C returns to the idle state. If arbitration is lost during the transmission of an
2
C switches to SLAVE mode so that it can recognize its own slave address or
2
2
C checks that each transmitted logic 1 appears on the I
C bus drives the clock line when the I
2
C stretches the clock after each byte transfer until the
2
C bus clock. The High period of the clock is
2
Product Specification
C is in MASTER mode,
I
2
C Serial I/O Interface
2
C bus can be
2
C bus as
139
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