MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet - Page 28
MC68HC000EI16
Manufacturer Part Number
MC68HC000EI16
Description
IC MPU 32BIT 16MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Specifications of MC68HC000EI16
Processor Type
M680x0 32-Bit
Speed
16MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Family Name
M68000
Device Core
ColdFire
Device Core Size
16/32Bit
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC000EI16
Manufacturer:
TI
Quantity:
604
Company:
Part Number:
MC68HC000EI16
Manufacturer:
FREESCALE
Quantity:
2 900
Company:
Part Number:
MC68HC000EI16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68HC000EI16R2
Manufacturer:
FREESCAL
Quantity:
8 831
Company:
Part Number:
MC68HC000EI16R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
NOTE: d is direction, L or R.
2-14
Opcode
TRAPV
SUBQ
SWAP
SBCD
STOP
SUBA
SUBX
TRAP
UNLK
SUBI
RTE
RTR
RTS
SUB
TAS
Scc
TST
Destination – Immediate Data
If supervisor state
else TRAP
(SP)
(SP)
(SP)
Destination 10 – Source 10 – X
If condition true
else 0s
If supervisor state
else TRAP
Destination – Source
Destination – Source
Destination – Immediate Data
Destination – Source – X
Register [31:16]
Destination Tested
SSP – 2
SSP – 4
SR
If V then TRAP
Destination Tested
An
then Immediate Data
Destination
then (SP)
SP + 4
restore state and deallocate stack according to (SP)
then 1s
SP; (SP)
(SSP); Vector Address
M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
CCR; SP + 2
PC; SP + 4
PC; SP + 4
Table 2-2. Instruction Set Summary (Sheet 4 of 4)
Destination
SSP; PC
SP;
SSP; Format/Offset
Destination
SR; SP + 2
An; SP + 4
Register [15:0]
SP
SP
Condition Codes; 1
Condition Codes
SP;
(SSP); SSP–2
Destination
Destination
Operation
SR; STOP
Destination
SP; (SP)
SP
PC
Destination
Destination
Destination
(SSP);
PC;
SSP;
bit 7 of
SUBI # <data>,<ea>
SUBQ # <data>,<ea>
RTE
RTR
RTS
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
Scc <ea>
STOP # <data>
SUB <ea>,Dn
SUB Dn,<ea>
SUBA <ea>,An
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP Dn
TAS <ea>
TRAP # <vector>
TRAPV
TST <ea>
UNLK An
S y n t a x
MOTOROLA