SPC5200CVR400B Freescale Semiconductor, SPC5200CVR400B Datasheet

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... S and AC97 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008, 2010. All rights reserved. Document Number: MPC5200BDS – Full duplex SPI mode – IrDA mode from 2400 bps to 4 Mbps • ...

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... Pull-up Requirements for the PCI Control Lines 66 3.3.3 Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM 3.3.4 .Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit Mode 3.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.1 JTAG_TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.2 e300 COP/BDM Interface . . . . . . . . . . . . . . . . 67 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MPC5200B Data Sheet, Rev Freescale Semiconductor ...

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Figure 1 shows a simplified MPC5200B block diagram. 603 e300 Core JTAG / COP Interface SRAM 16 KB Reset / Clock Generation CommBus PSC 6x SDRAM/DDR Systems Interface Unit (SIU) SDRAM/DDR Memory Controller BestComm DMA 2 SPI Ethernet I C ...

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... V –0.3 2.1 V –0.3 VDD_IO + 0.3 V –0.3 VDD_MEM_IO V + 0.3 — 1.0 V — 1 –55 150 C (1) (1) Max Unit 1.58 V 3.6 V 3.6 V 2.63 V 1.58 V 1.58 V Freescale Semiconductor D1.1 D1.2 D1.3 D1.4 D1.5 D1.6 D1.7 D1.8 D1.9 SpecID D2.1 D2.2 D2.3 D2.4 D2.5 D2.6 ...

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... Input high voltage Input high voltage Input low voltage VDD_IO/VDD_MEM_IO Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input leakage current VDD_IO/VDD_IO_MEM Input leakage current Freescale Semiconductor Sym Min Vin Vin SDR Vin DDR ( Table 3 ...

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... Min Max Unit SpecID μA — ±10 D3.15 μA 40 109 D3.16 μA 41 111 D3.17 μA 36 106 D3.18 2.4 — V D3.19 1.7 — V D3.20 — 0.4 V D3.21 — 0.4 V D3.22 –1.0 1.0 mA D3.23 — D3.24 I Unit SpecID D3. D3. D3. D3. D3. D3.30 Freescale Semiconductor ...

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... N is the number of output pins switching in a group the capacitance per pin, VDD_IO is the IO voltage swing the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200B processor must not exceed the value, which would cause the maximum junction temperature to be exceeded. Freescale Semiconductor CAUTION Rating ...

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... Core Power Supply (VDD_CORE) 33/132/66/132/396 Typ 1080 600 225 225 52.5 Typ 2 Typ 33 MPC5200B Data Sheet, Rev. 4 SpecID Unit Notes (1),(2) mW D5.1 (1),(3) mW D5.2 (1),(4) mW D5.3 (1),(5) mW D5.4 (1),(6) mW D5.5 Unit Notes ( Unit Notes (9) mW D5 °C SDR Freescale Semiconductor ...

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... Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: Freescale Semiconductor Table 7. Thermal Resistance Data Board Layers ...

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... The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration θ θ θ Ψ × MPC5200B Data Sheet, Rev. 4 Eqn. 4 Eqn. 5 Freescale Semiconductor ...

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... PLL has been disabled and subsequently re-enabled during sleep modes. 1.2.4 e300 Core PLL Electrical Characteristics The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Freescale Semiconductor Sym Notes Min Typical f 15 ...

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... GPIOs and Timers • IEEE 1149.1 (JTAG) AC Specifications MPC5200B Data Sheet, Rev. 4 Typical Max Unit SpecID — 550 MHz O4.1 — 40.0 ns O4.2 — 1200 MHz O4.3 — 367 MHz O4.4 — 50.0 ns O4.5 — 150 ps O4.6 μs — 100 O4.7 Freescale Semiconductor ...

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... CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0–6] settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200B User’s Manual (MPC5200BUM). 2 SYS_XTAL_IN duty cycle is measured at V Freescale Semiconductor Table 12. Clock Frequencies Min — — ...

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... NOTE Table 15. Reset Rise/Fall Timing Min — — — — — — NOTE MPC5200B Data Sheet, Rev. 4 Table 14 Reference Clock SpecID SYS_XTAL_IN A3.1 SYS_XTAL_IN A3.2 SYS_XTAL_IN A3.3 Max Unit SpecID A3.9 Freescale Semiconductor ...

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... Four IRQ interrupts • Eight GPIO interrupts with simple interrupt capability (not available in power-down mode) • Eight WakeUp interrupts (special GPIO pins) The propagation of these three kinds of interrupts to the core is shown in the following graphic: Freescale Semiconductor 4096 clocks sample sample sample sample sample ...

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... IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) Freescale Semiconductor SpecID A4.1 A4.2 A4.3 A4.4 A4.5 A4.6 A4.7 A4.8 A4.9 A4.10 A4.11 A4.12 A4.13 A4.15 A4 ...

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... DQM valid after rising edge of MEM_CLK valid DM DQM hold after rising edge of MEM_CLK hold data MDQ setup to rising edge of MEM_CLK setup data MDQ hold after rising edge of MEM_CLK hold Freescale Semiconductor Min Pulse Width Max Pulse Width > 1 clock cycle — Min 7.5 — t mem_clk t × ...

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... MPC5200B Data Sheet, Rev. 4 NOP NOP NOP NOP data hold Max Units SpecID — ns A5.8 t × 0.5 + 0.4 ns A5.9 mem_clk — ns A5.10 t × 0.25 + 0.4 ns A5.11 mem_clk — ns A5.12 t × 0.75 + 0.4 ns A5.13 mem_clk — ns A5.14 Freescale Semiconductor ...

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... MEM_CLK t Control Signals, Address and MBA hold hold after rising edge of MEM_CLK data Setup time relative to MDQS setup data Hold time relative to MDQS hold Freescale Semiconductor t hold Active NOP WRITE NOP DM DM hold valid data data ...

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... Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing 20 t hold NOP READ NOP NOP t data_valid_min t data_sample_min t data_valid_min × t 0.5 MEM_CLK t hold Column t hold MPC5200B Data Sheet, Rev. 4 NOP NOP NOP t data_valid_max Sample position A t data_sample_max t data_valid_max Sample position t data_sample_min t data_sample_max Freescale Semiconductor B ...

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... The MPC5200B is always the source of the PCI CLK. The clock waveform must be delivered to each 33 MHz or 66 MHz PCI component in the system. Figure 9 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications. Freescale Semiconductor Min 7.5 — 1.0 1.0 Write ...

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... Notes Max (1),(3) — ns — ns — — ns — ( V/ns — 200 ps — 33 MHz Units Notes Max (1),(2),( (1),(2),( (1) — (3),(4) — ns (3),(4) — ns (4) — ns Freescale Semiconductor SpecID A6.1 A6.2 A6.3 A6.4 — SpecID A6.5 A6.6 A6.7 A6.8 A6.9 A6.10 A6.11 ...

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... OE assertion before CS assertion negation before CS negation valid before CS assertion hold after CS negation 7 t DATA output valid before CS assertion 8 t DATA output hold after CS negation 9 Freescale Semiconductor t PCIck t IPBIck Table 24. Non-MUXed Mode Timing Min 4.6 2 WS) × WS) × t PCIck t IPBIck t IPBIck — ...

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... PCIck — 6 PCIck PCIck t IPBIck t IPBIck — 2.0 — 4.4 MPC5200B Data Sheet, Rev. 4 Units Notes SpecID — ns — A7.12 (6) ns A7.13 PCIck (3) — ns A7.14 (3) ns A7.15 (4) ns A7.16 (4) ns A7.17 (5) — ns A7.18 (5) — ns A7.19 (1) ns A7.20 (1) ns A7.21 Freescale Semiconductor ...

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... CS pulse width 1 t ADDR valid before CS assertion 2 t ADDR hold after CS negation assertion before CS assertion negation before CS negation valid before CS assertion hold after CS negation 7 t DATA setup before rising edge of 8 PCI clock Freescale Semiconductor Table 25. Burst Mode Timing Min 4.6 2 × ...

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... Figure 12. Timing Diagram—Burst Mode MPC5200B Data Sheet, Rev. 4 Max Units Notes SpecID — ns — (4) ( × PCIck ( × — PCIck (3) 7 (2),(3) × 2 × (32/DS) × PCIck 2.5 ns — — PCIck Freescale Semiconductor A7.32 A7.33 A7.34 A7.35 A7.36 A7.37 A7.38 ...

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... ACK is input and can be used to shorten the CS pulse width. 3. Deadcycles are only used arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules. Freescale Semiconductor Table 26. MUXed Mode Timing Min Max 4 ...

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... Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold time beyond that required by the ATA-4 specification Data tenure Figure 13. Timing Diagram—MUXed Mode MPC5200B Data Sheet, Rev Data Data Data Data Data Freescale Semiconductor ...

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... DIOW data hold 4 t DIOR data setup 5 t DIOR data hold 6 t DIOR/DIOW to address 9 valid hold t IORDY setup A t IORDY pulse width B Freescale Semiconductor NOTE Table 27. PIO Mode Timing Specifications Min/Max Mode 0 Mode 1 (ns) (ns) (ns) min 600 383 min 70 50 min 165 125 ...

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... MPC5200B Data Sheet, Rev Mode 1(ns) Mode 2(ns) SpecID 150 120 A8.12 — — A8. A8. A8. A8. A8. A8. A8. A8. A8. A8. A8. A8.24 Freescale Semiconductor ...

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... DVS t 6 — 6 DVH t 0 230 150 — 20 MLI t 0 — Freescale Semiconductor Figure 15. Multiword DMA Timing NOTE Table 29. Ultra DMA Timing Specification MODE 2 (ns) Max Min Max — 55 — Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge — ...

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... Time from STROBE edge to negation of DMARQ or assertion of STOP, when sender terminates a burst. after negation of DMARDY. STROBE and DMARDY timing measurements are taken at MPC5200B Data Sheet, Rev. 4 Comment SpecID A8.36 A8.37 A8.38 A8.39 A8.40 A8.41 A8.42 A8.43 A8.44 A8.45 negation. A8.46 Freescale Semiconductor ...

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... DD(0:15) DA0, DA1, DA2, CS[0:1]1 Figure 16. Timing Diagram—Initiating an Ultra DMA Data In Burst DSTROBE at device t DVH DD(0:15) at device DSTROBE at host t DD(0:15) at host Figure 17. Timing Diagram—Sustained Ultra DMA Data In Burst Freescale Semiconductor ACK ENV t ZAD t t ACK ENV t ZAD t ZIORDY ...

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... Figure 18. Timing Diagram—Host Pausing an Ultra DMA Data In Burst DMARQ (device) DMACK (host) STOP (host) HDMARDY (host DSTROBE (device) DD[0:15] DA0,DA1,DA2, CS[0:1] Figure 19. Timing Diagram—Drive Terminating Ultra DMA Data In Burst RFS MLI ZAH t DVS t AZ MPC5200B Data Sheet, Rev ACK t ACK t IORDYZ t DVH CRC t ACK Freescale Semiconductor ...

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... DD[0:15] DA0,DA1,DA2, CS[0:1] Figure 20. Timing Diagram—Host Terminating Ultra DMA Data In Burst DMARQ (device) DMACK (host) STOP (host) DDMARDY (host) HSTROBE (device) DD[0:15] (host) DA0,DA1,DA2, CS[0:1] Figure 21. Timing Diagram—Initiating an Ultra DMA Data Out Burst Freescale Semiconductor ZAH ENV t ACK ZIORDY ...

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... Figure 22. Timing Diagram—Sustained Ultra DMA Data Out Burst DMARQ (device) DMACK (host) STOP (host) DDMARDY (device) HSTROBE DD[0:15] (host) Figure 23. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst 36 t 2CYC t t CYC CYC t DVS t DVH RFS MPC5200B Data Sheet, Rev 2CYC t DVS t DVH t DH Freescale Semiconductor ...

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... CS[0:1] Figure 24. Timing Diagram—Host Terminating Ultra DMA Data Out Burst DMARQ (device) DMACK (host) STOP (host) DDMARDY (device) HSTROBE (host) DD[0:15] (host) DA0,DA1,DA2, CS[0:1] Figure 25. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst Freescale Semiconductor DVS RFS LI MPC5200B Data Sheet, Rev. 4 ...

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... Table 31. MII Rx Signal Timing Min 10 10 35% 35 MPC5200B Data Sheet, Rev. 4 Min Max Units 7 — IP Bus cycles — Bus cycles 2 Max Unit — ns — ns (1) 65% RX_CLK Period (1) 65% RX_CLK Period t 4 Freescale Semiconductor SpecID A8.48 A8.49 SpecID A9.1 A9.2 A9.3 A9.4 ...

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... TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification. TX_CLK (Input) TXD[3:0] (Outputs) TX_EN TX_ER Figure 28. Ethernet Timing Diagram—MII Tx Signal Sym Description t CRS, COL minimum pulse width 9 Figure 29. Ethernet Timing Diagram—MII Async Freescale Semiconductor Table 32. MII Tx Signal Timing Min 5 — 35% 35 ...

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... Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 4 Max Unit SpecID 25 ns — ns — ns — ns — ns — ns Min Max Units SpecID 83.3 667 ns 83.3 667 ns — 7.9 ns — 7.9 ns Freescale Semiconductor A9.10 A9.11 A9.12 A9.13 A9.14 A9.15 A10.1 A10.2 A10.3 A10.4 ...

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... Input Data hold time 8 Slave disable lag time 9 Sequential transfer delay 10 Clock falling time 11 Clock rising time 1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM). Freescale Semiconductor Description Cycle time NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 4 ...

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... NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev Max Units SpecID (1) 1024 IP-Bus Cycle A11.12 (1) 512 IP-Bus Cycle A11.13 — ns A11.14 50.0 ns A11.15 50.0 ns A11.16 — ns A11.17 — ns A11.18 — ns A11.19 (1) — IP-Bus Cycle A11.20 Freescale Semiconductor ...

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... Input Data hold time 7 Slave disable lag time 8 Sequential Transfer delay 9 Clock falling time 10 Clock rising time 1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM). Freescale Semiconductor Description Cycle time NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 4 ...

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... Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev Min Max Units SpecID (1) 4 1024 IP-Bus Cycle A11.31 (1) 2 512 IP-Bus Cycle A11.32 15.0 — ns A11.33 — 50.0 ns A11.34 50.0 — ns A11.35 0.0 — ns A11.36 15.0 — ns A11.37 (1) 1 — IP-Bus Cycle A11.38 Freescale Semiconductor ...

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... Clock high time 7 Data setup time 8 Start condition setup time (for repeated start condition 9 Stop condition setup time 1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM). Freescale Semiconductor Input Timing Specifications—SCL and SDA Description Clock low time ...

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... IP-Bus Cycle A13.8 (3) 10 — IP-Bus Cycle A13.9 — 7.9 ns A13.10 (3) 7 — IP-Bus Cycle A13.11 — 7.9 ns A13.12 (3) 10 — IP-Bus Cycle A13.13 (3) 2 — IP-Bus Cycle A13.14 (3) 20 — IP-Bus Cycle A13.15 (3) 10 — IP-Bus Cycle A13. Freescale Semiconductor ...

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... BitClk (CLKPOL=0) Output BitClk (CLKPOL=1) Output 5 FrameSync (SyncPol = 1) Output FrameSync (SyncPol = 0) Output TxD Output RxD Input Figure 37. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC / I Freescale Semiconductor 2 S Mode 40.0 NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet, Rev ...

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... Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet, Rev Slave Mode Typ Max Units — — ns (1) — 50 — % — — ns — — 14.0 ns — — ns — — Slave Mode Freescale Semiconductor SpecID A15.9 A15.10 A15.11 A15.12 A15.13 A15.14 ...

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... Table 45. Timing Specifications — IrDA Transmit Line Sym 1 Pulse high time, defined in the IrDA protocol definition 2 Pulse low time, defined in the IrDA protocol definition 3 4 Transmitter falling time Freescale Semiconductor NOTE Output timing is specified at a nominal 50 pF load Figure 39. Timing Diagram — AC97 Mode ...

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... MPC5200B Data Sheet, Rev. 4 Min Max Units SpecID 30.0 — ns A15.26 15.0 — ns A15.27 30.0 — ns A15.28 — 8.9 ns A15.29 — 8.9 ns A15.30 6.0 — ns A15.31 1.0 — ns A15.32 — 8.9 ns A15.33 15.0 — ns A15.34 — 7.9 ns A15.35 — 7.9 ns A15.36 Freescale Semiconductor ...

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... SCK cycle time, programable in the PSC CCS register 2 SCK pulse width, 50% SCK duty cycle 3 Slave select clock delay Output data valid after SS 7 Output data valid after SCK 8 9 Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time Freescale Semiconductor Description Input Data setup time ...

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... Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev Min Max Units SpecID 30.0 — ns A15.46 15.0 — ns A15.47 30.0 — ns A15.48 — 8.9 ns A15.49 6.0 — ns A15.50 1.0 — ns A15.51 — 8.9 ns A15.52 15.0 — ns A15.53 — 7.9 ns A15.54 — 7.9 ns A15.55 Freescale Semiconductor ...

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... Sym 1 SCK cycle time, programable in the PSC CCS register 2 SCK pulse width, 50% SCK duty cycle 3 Slave select clock delay Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time Freescale Semiconductor Description Output data valid Input Data setup time Input Data hold time ...

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... Table 50 gives the timing specifications. Table 50. Asynchronous Signals Description Clock Period Input Setup Input Hold Output Valid Output Hold MPC5200B Data Sheet, Rev Min Max Units SpecID 7.52 — ns A16.1 12 — ns A16.2 1 — ns A16.3 — 15.33 ns A16.4 1 — ns A16.5 Freescale Semiconductor ...

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... Output Input Figure 45. Timing Diagram—Asynchronous Signals Freescale Semiconductor valid valid MPC5200B Data Sheet, Rev ...

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... Figure 47. Timing Diagram—JTAG TRST MPC5200B Data Sheet, Rev. 4 Min Max Unit SpecID 0 25 MHz 40 — ns 1.08 — — — — — — — Table 51. Numbers shown reference Table 51. Freescale Semiconductor A17.1 A17.2 A17.3 A17.4 A17.5 A17.6 A17.7 A17.8 A17.9 A17.10 A17.11 A17.12 A17.13 A17.14 ...

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... Package Parameters The MPC5200B uses TE-PBGA package. The package parameters are as provided in the following list: • Package outline • Interconnects: 2 • Pitch: 1.27 mm Freescale Semiconductor INPUT DATA VALID 8 OUTPUT DATA VALID 9 Numbers shown reference 10 INPUT DATA VALID 12 OUTPUT DATA VALID ...

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... ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS DIM MIN MAX A 2.05 2.65 A1 0.50 0.70 A2 0.50 0.70 A3 1.05 1.25 b 0.60 0.90 D 27.00 BSC D1 24.13 REF D2 23.30 24.70 E 27.00 BSC E1 24.13 REF E2 23.30 24.70 e 1.27 BSC SIDE VIEW B C DATE 10/15/1997 Freescale Semiconductor ...

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... EXT_AD[31:0] PCI_CBE_0 PCI_CBE_1 PCI_CBE_2 PCI_CBE_3 PCI_CLOCK PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_IRDY PCI_PAR PCI_PERR PCI_REQ PCI_RESET PCI_SERR PCI_STOP Freescale Semiconductor Table 52. MPC5200B Pinout Listing Output Driver Type Power Supply SDRAM I/O VDD_MEM_IO DRV16_MEM I/O VDD_MEM_IO DRV16_MEM I/O VDD_MEM_IO DRV16_MEM I/O VDD_MEM_IO DRV16_MEM ...

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... MPC5200B Data Sheet, Rev. 4 Input Pull-up/ Type down PCI TTL PULLUP TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL PULLDOWN TTL PULLDOWN TTL PULLUP TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Freescale Semiconductor ...

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... USB_RXD USB_4 USB_RXP USB_5 USB_RXN USB_6 USB_PRTPWR USB_7 USB_SPEED USB_8 USB_SUPEND USB_9 USB_OVRCNT I2C_0 SCL I2C_1 SDA I2C_2 SCL Freescale Semiconductor Output Driver Type Power Supply Type I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO ...

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... I/O VDD_IO DRV8 I/O VDD_IO DRV4 MPC5200B Data Sheet, Rev. 4 Input Pull-up/ Type down Schmitt TTL TTL TTL Schmitt TTL TTL TTL TTL Schmitt TTL TTL TTL Schmitt TTL TTL TTL TTL TTL TTL TTL TTL PULLUP_MEM TTL TTL Freescale Semiconductor ...

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... IRQ1 IRQ2 IRQ3 SYS_PLL_TPA TEST_MODE_0 TEST_MODE_1 TEST_SEL_0 TEST_SEL_1 JTAG_TCK TCK JTAG_TDI TDI JTAG_TDO TDO JTAG_TMS TMS JTAG_TRST TRST VDD_IO Freescale Semiconductor Output Driver Type Power Supply Type I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO ...

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... Note: Use 1 microsecond or slower rise time for all supplies. 64 Output Driver Type Power Supply — — — — — Figure 51. Supply Voltage Sequencing MPC5200B Data Sheet, Rev. 4 Input Pull-up/ Type Type down VDD_IO, VDD_IO_MEM (SDR) VDD_IO_MEM (DDR) VDD_CORE, PLL_AVDD Time Freescale Semiconductor ...

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... Pull-up/Pull-down Resistor Requirements The MPC5200B requires external pull-up or pull-down resistors on certain pins. 3.3.1 Pull-down Resistor Requirements for TEST pins The MPC5200B requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1. Freescale Semiconductor < 1 Ω 10 Ω 10 μF 200–400 pF Figure 52. Power Supply Filtering MPC5200B Data Sheet, Rev ...

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... For more details refer to the Reset and JTAG Timing Specification. PORRESET Required assertion of JTAG_TRST JTAG_TRST 3.4.1.2 Connecting JTAG_TRST The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below) 66 Figure 53. PORRESET vs. JTAG_TRST MPC5200B Data Sheet, Rev. 4 Optional assertion of JTAG_TRST Freescale Semiconductor ...

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... CORE_QACK to GND in its normal/functional mode (always asserted). For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended. Freescale Semiconductor Table 53 gives the COP/BDM interface signals. The pin order Table 53 ...

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... TCK 7 (2) VDD 6 10Kohm TDI 3 CKSTP_OUT 15 TDO 1 halted ( qack ( Figure 54. COP Connector Diagram MPC5200B Data Sheet, Rev. 4 PORRESET MPC5200B HRESET VDD VDD SRESET VDD JTAG_TRST VDD JTAG_TMS VDD JTAG_TCK VDD JTAG_TDI TEST_SEL_0 JTAG_TDO Figure 55 shows the connection Freescale Semiconductor ...

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... Figure 55. JTAG_TRST Wiring for Boards without COP Connector 4 Ordering Information 1 Part Number MPC5200VR400B MPC5200CVR466B SPC5200CBV400B SPC5200CVR400B SC103335VR400B 1 Shipped in trays. Add “R2” suffix for Tape & Reel. 2 Commercial Qualified to < 250 PPM level. Industrial/Automotive Qualified to AEC-Q100. Automotive has Zero Defect flow. 3 Standard is halide-free with Pb solder balls ...

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... Added description for PCI CLK Slew Rate for PCI CLK Specifications table. Added description for minimum rates in the DDR SDRAM Memory Write Timing table. 3 Added one item to table “DDR SDRAM Memory Read Timing.” 4 Updated table “Ordering Information.” 70 Table 55. Document Revision History Differences MPC5200B Data Sheet, Rev. 4 Freescale Semiconductor ...

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... Freescale Semiconductor MPC5200B Data Sheet, Rev ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...