MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 608
MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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DUART
13.3.1.8
The UMCRs control the interface with the external peripheral device on the UART bus.
Figure 13-10
Table 13-15
.
13-14
Bits
0–2
4–5
3
6
7
Offset 0x504
Reset
Name
LOOP Local loopback mode.
RTS
W
—
—
—
R
0x604
describes the fields of UMCRs.
shows the bits in the UMCRs
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved.
0 Normal operation
1 Functionally, the data written to UTHR can be read from URBR of the same UART, and UMCR[RTS] is tied
Reserved.
Ready to send.
0 Negates corresponding UART_RTS output
1 Assert corresponding UART_RTS output. Informs external modem or peripheral that the UART is ready for
Reserved.
Table 13-14. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS]
Modem Control Registers (UMCR0, UMCR1)
to UMSR[CTS].
sending/receiving data
0
—
Figure 13-10. Modem Control Register (UMCR)
Table 13-15. UMCR Field Descriptions
PEN
0
0
0
0
1
1
1
1
2
SP
0
0
1
1
0
0
1
1
LOOP
EPS
0
1
0
1
0
1
0
1
3
All zeros
Description
Parity Selected
Space parity
Even parity
Mark parity
Odd parity
No parity
No parity
No parity
No parity
4
—
5
Freescale Semiconductor
RTS
Access: Read/Write
6
—
7
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