MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 713
MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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To improve the timing margins a PLL is used to generate external clocks, which minimize the skew
between the local bus and the memory clock.
PLL.
14.5.4.4
Contrary to older DRAM technologies, SDRAM devices typically are organized either x4, x8, x16, or x32.
There are no mainstream devices that include parity support. To allow for error protection on the local bus
an additional SDRAM for the 4 parity bits must be used. Since the local bus allows for SDRAM accesses
with less than the full port size, read-modify-write cycles are supported for SDRAM write cycles.
Freescale Semiconductor
LBC output signals on pins
RBC (reference bus clock)
LSYNC_IN
LSYNC_OUT
LCLK
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Parity Support for SDRAM
Figure 14-77. Local Bus PLL Operation
t
D
= t
PLL
Figure 14-77
+t
P
t
P
t
L
shows relative timings for the local bus clock
Local Bus Controller
14-95
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