MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 8
MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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Price
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MPC8533EVTANGA
Manufacturer:
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Quantity:
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- MPC8533VTALF PDF datasheet
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Paragraph
Number
4.4.4
4.4.4.1
4.4.4.2
4.4.4.2.1
4.4.4.3
4.4.4.4
5.1
5.1.1
5.1.2
5.2
5.3
5.3.1
5.4
5.5
5.5.1
5.5.2
5.5.3
5.6
5.7
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.9
5.9.1
5.9.2
5.9.3
5.9.4
5.10
5.10.1
5.10.2
5.10.3
viii
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Overview.......................................................................................................................... 5-1
e500 Processor and System Version Numbers................................................................. 5-4
Features ............................................................................................................................ 5-5
Instruction Set ................................................................................................................ 5-11
Instruction Flow ............................................................................................................. 5-13
Programming Model ...................................................................................................... 5-16
On-Chip Cache Implementation .................................................................................... 5-18
Interrupts and Exception Handling ................................................................................ 5-18
Memory Management.................................................................................................... 5-22
Memory Coherency ....................................................................................................... 5-26
Clocking..................................................................................................................... 4-21
Upward Compatibility ................................................................................................. 5-3
Core Complex Summary ............................................................................................. 5-3
e500v2 Differences .................................................................................................... 5-10
Initial Instruction Fetch.............................................................................................. 5-13
Branch Detection and Prediction ............................................................................... 5-13
e500 Execution Pipeline ............................................................................................ 5-14
Exception Handling ................................................................................................... 5-18
Interrupt Classes ........................................................................................................ 5-19
Interrupt Types ........................................................................................................... 5-19
Upper Bound on Interrupt Latencies ......................................................................... 5-20
Interrupt Registers...................................................................................................... 5-20
Address Translation ................................................................................................... 5-24
MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)..................................... 5-25
Process ID Registers (PID0–PID2)............................................................................ 5-26
TLB Coherency.......................................................................................................... 5-26
Atomic Update Memory References ......................................................................... 5-27
Memory Access Ordering.......................................................................................... 5-27
Cache Control Instructions ........................................................................................ 5-27
System Clock/PCI Clock ....................................................................................... 4-21
PCI Express ........................................................................................................... 4-22
Ethernet Clocks...................................................................................................... 4-23
Real Time Clock .................................................................................................... 4-23
Minimum Frequency Requirements .................................................................. 4-22
e500 Core Complex and L2 Cache
Core Complex Overview
Contents
Chapter 5
Part II
Title
Freescale Semiconductor
Number
Page
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