MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 240
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
- Current page: 240 of 962
- Download datasheet (4Mb)
CPU32+
5.7.2.11 CONDITIONAL BRANCH INSTRUCTIONS. The conditional branch instruction
timing table indicates the number of clock periods needed for the processor to perform the
specified branch on the given branch size, with complete execution times given. No addi-
tional tables are needed to calculate total effective execution time for these instructions. The
total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/
p/w) are included in the total clock cycle number. All timing data assumes two-clock reads
and writes.
5-98
BCHG
BCHG
BCHG
BCHG
BCLR
BCLR
BCLR
BCLR
BSET
BSET
BSET
BSET
BTST
BTST
BTST
BTST
Timing is calculated with the CPU32+ in 16-bit mode.
Bcc
Bcc.B
Bcc.W
Bcc.L
DBcc
DBcc
DBcc
DBcc
DBcc
DBcc
Timing is calculated with the CPU32+ in 16-bit mode.
An # fetch EA time must be added for this instruction: FEA
In loop mode
#, Dn
Dn, Dm
#, FEA
Dn, FEA
#, Dn
Dn, Dm
#, FEA
Dn, FEA
#, Dn
Dn, Dm
#, FEA
Dn, FEA
#, Dn
Dn, Dm
#, FEA
Dn, FEA
(taken)
(not taken)
(not taken)
(not taken)
(T, not taken)
(F, 1, not taken)
(F, not 1, taken)
(T, not taken)
(F, 1, not taken)
(F, not 1, taken)
Instruction
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Head
Head
2
4
1
2
2
4
1
2
2
4
1
2
2
2
1
2
2
2
0
0
1
2
6
4
6
6
Tail
Tail
0
0
2
2
0
0
2
2
0
0
2
2
0
0
0
0
0
0
0
1
0
0
0
0
2
2
FEA
OPER
10(0/0/0)
10(0/2/0)
6(0/2/0)
8(0/2/1)
6(0/2/0)
8(0/2/1)
6(0/2/0)
8(0/2/1)
4(0/2/0)
4(0/2/0)
6(0/1/0)
8(0/1/0)
6(0/1/0)
8(0/1/1)
6(0/1/0)
8(0/1/1)
6(0/1/0)
8(0/1/1)
4(0/1/0)
8(0/1/0)
8(0/2/0)
4(0/1/0)
4(0/2/0)
6(0/3/1)
4(0/2/0)
6(0/2/0)
Cycles
Cycles
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