MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 564
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
- Current page: 564 of 962
- Download datasheet (4Mb)
Serial Communication Controllers (SCCs)
The following pins take on new meanings when the Ethernet protocol is selected for the
SCC:
The EEST has similar names for its connection to the seven basic QUICC pins. In addition,
the EEST contains a loopback pin to allow the QUICC to perform external loopback testing.
This can be controlled by any available parallel I/O pin on the QUICC.
7-240
1. Transmit Enable (TENA). The SCC’s RTS pin changes to become TENA when the
2. Receive Enable (RENA). The SCC’s CD pin changes to become RENA when the SCC
3. Collision (CLSN). The SCC’s CTS pin changes to become CLSN when the SCC is
NOTE: Short transmit frames are padded automatically by the QUICC.
SCC is configured for Ethernet operation. The polarity of TENA is active high; where-
as, the polarity of RTS is active low.
is configured for Ethernet operation. The polarity of RENA is active high; whereas, the
polarity of CD is active low.
configured for Ethernet operation. The polarity of CLSN is active high; whereas, the
polarity of CTS is active low.
PREAMBLE
7 BYTES
The carrier sense signal is often referred to in Ethernet descrip-
tions, because it defines whether the LAN is currently in use.
Carrier sense is defined as RENA ORed with CLSN.
DELIMITER
Figure 7-67. Connecting the QUICC to Ethernet
1 BYTE
FRAME
START
QUICC
SCC
PARALLEL I/O
RCLK (CLKx)
Freescale Semiconductor, Inc.
TCLK (CLKx)
TENA (RTS)
CLSN (CTS)
RENA (CD)
For More Information On This Product,
6 BYTES
RXD
TXD
ADDR.
DEST.
STORED IN TRANSMIT BUFFER
MC68360 USER’S MANUAL
STORED IN RECEIVE BUFFER
Go to: www.freescale.com
6 BYTES
SOURCE
ADDR.
NOTE
2 BYTES
LENGTH
TYPE/
TX
TENA
TCLK
RX
RENA
RCLK
CLSN
LOOP
MC68160
EEST
46–1500 BYTES
DATA
RJ-45
D-15
TWISTED PAIR
AUI
SEQUENCE
4 BYTES
FRAME
CHECK
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