MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet
MC68EN360CAI25L
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... Freescale Semiconductor, Inc. MC68360 QUad Integrated Communications Controller User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. ii For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. The complete documentation package for the MC68360 consists of the MC68360UM/AD, MC68360 QUad Integrated Communications Controller User’s Manual , M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68360/D, MC68360 QUad Integrated Communications Controller Product Brief . The MC68360 QUad Integrated Communications Controller User’s Manual describes the programming, capabilities, registers, and operation of the MC68360 and the MC68EN360 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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... Freescale Semiconductor, Inc. Paragraph Number 1.1 QUICC Key Features .............................................................................. 1-1 1.2 QUICC Architecture Overview................................................................. 1-4 1.2.1 CPU32+ Core.......................................................................................... 1-5 1.2.2 System Integration Module (SIM60)........................................................ 1-5 1.2.3 Communications Processor Module (CPM) ............................................ 1-6 1.3 Upgrading Designs from the MC68302 ................................................... 1-6 1.3.1 Architectural Approach ............................................................................ 1-6 1 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 2.1.7.5 Transfer Size (SIZ1, SIZ0). ......................................................................2-8 2.1.7.6 Read/Write (R/W).....................................................................................2-8 2.1.7.7 Output Enable/Address Multiplex (OE/AMUX).........................................2-9 2.1.7.8 Byte Write Enable (WE3–WE0). ..............................................................2-9 2.1.8 Bus Arbitration Signals.............................................................................2-9 2.1.8.1 Bus Request (BR). ...................................................................................2-9 2.1.8.2 Bus Grant (BG). .......................................................................................2-9 2 ...
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... Freescale Semiconductor, Inc. Paragraph Number 3.1 Dual-Port RAM Memory Map .................................................................. 3-2 3.2 CPM Sub-Module Base Addresses......................................................... 3-3 3.3 Internal Registers Memory Map .............................................................. 3-4 3.3.1 SIM Registers Memory Map.................................................................... 3-4 3.3.2 CPM Registers Memory Map .................................................................. 3-6 4.1 Bus Transfer Signals ............................................................................... 4-2 4.1.1 Bus Control Signals ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 4.6 Bus Arbitration .......................................................................................4-49 4.6.1 Bus Request ..........................................................................................4-52 4.6.2 Bus Grant...............................................................................................4-53 4.6.3 Bus Grant Acknowledge ........................................................................4-53 4.6.4 Bus Arbitration Control...........................................................................4-54 4.6.5 Slave (Disable CPU32+) Mode Bus Arbitration .....................................4-55 4.6.6 Slave (Disable CPU32+) Mode Bus Exceptions ....................................4-59 4 ...
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... Freescale Semiconductor, Inc. Paragraph Number 5.3.4.3 Table Example 3: 8-Bit Independent Variable....................................... 5-30 5.3.4.4 Table Example 4: Maintaining Precision ............................................... 5-32 5.3.4.5 Table Example 5: Surface Interpolations .............................................. 5-33 5.3.5 Nested Subroutine Calls........................................................................ 5-33 5.3.6 Pipeline Synchronization with the NOP Instruction ............................... 5-34 5.4 Processing States ................................................................................. 5-34 5 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 5.5.4.1 Four-Word Stack Frame ........................................................................5-56 5.5.4.2 Six-Word Stack Frame...........................................................................5-56 5.5.4.3 Bus Error Stack Frame ..........................................................................5-56 5.6 Development Support ............................................................................5-59 5.6.1 CPU32+ Integrated Development Support ............................................5-59 5.6.1.1 Background Debug Mode (BDM) Overview...........................................5-59 5.6.1.2 Deterministic Opcode Tracking Overview ...
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... Freescale Semiconductor, Inc. Paragraph Number 5.7 Instruction Execution Timing ................................................................. 5-82 5.7.1 Resource Scheduling ............................................................................ 5-83 5.7.1.1 Microsequencer..................................................................................... 5-83 5.7.1.2 Instruction Pipeline ................................................................................ 5-83 5.7.1.3 Bus Controller Resources ..................................................................... 5-83 5.7.1.3.1 Prefetch Controller ................................................................................ 5-84 5.7.1.3.2 Write-Pending Buffer ............................................................................. 5-84 5.7.1.3.3 Microbus Controller ............................................................................... 5-85 5.7.1.4 Instruction Execution Overlap ............................................................... 5-85 5 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 6.5 SIM60 System Clock Generation...........................................................6-12 6.5.1 Clock Generation Methods ....................................................................6-12 6.5.2 Oscillator Prescaler (Divide by 128).......................................................6-13 6.5.3 Phase-Locked Loop (PLL) .....................................................................6-14 6.5.3.1 Frequency Multiplication ........................................................................6-14 6.5.3.2 Skew Elimination....................................................................................6-15 6.5.4 Low-Power Divider.................................................................................6-15 6 ...
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... Freescale Semiconductor, Inc. Paragraph Number 6.9.3.7 Periodic Interrupt Timer Register (PITR)............................................... 6-38 6.9.3.8 Software Service Register (SWSR)....................................................... 6-39 6.9.3.9 CLKO Control Register (CLKOCR) ....................................................... 6-39 6.9.3.10 PLL Control Register (PLLCR) .............................................................. 6-40 6.9.3.11 Clock Divider Control Register (CDVCR) .............................................. 6-42 6.9.3.12 Breakpoint Address Register (BKAR) ................................................... 6-44 6 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 7.3 Dual-Port RAM.........................................................................................7-8 7.3.1 Buffer Descriptors ..................................................................................7-10 7.3.2 Parameter RAM .....................................................................................7-10 7.4 RISC Timer Tables ................................................................................7-11 7.4.1 RISC Timer Table Parameter RAM .......................................................7-12 7.4.2 RISC Timer Table Entries ......................................................................7-14 7.4.3 RISC Timer Event Register (RTER) ......................................................7-14 7 ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.6.4.2.3 IDMA Commands (INIT_IDMA)............................................................. 7-38 7.6.4.3 Starting the IDMA .................................................................................. 7-38 7.6.4.4 Requesting IDMA Transfers .................................................................. 7-39 7.6.4.4.1 Internal Maximum Rate ......................................................................... 7-39 7.6.4.4.2 Internal Limited Rate ............................................................................. 7-39 7.6.4.4.3 External Burst Mode.............................................................................. 7-40 7.6.4.4.4 External Cycle Steal .............................................................................. 7-42 7.6.4.5 IDMA Bus Arbitration ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 7.8.5.2 SI Mode Register (SIMODE)..................................................................7-78 7.8.5.3 SI Clock Route Register (SICR).............................................................7-86 7.8.5.4 SI Command Register (SICMR).............................................................7-87 7.8.5.5 SI Status Register (SISTR) ....................................................................7-87 7.8.5.6 SI RAM Pointers (SIRP).........................................................................7-88 7.8.5.6.1 SIRP When RDM = 00 (One Static TDM) ..............................................7-89 7 ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.10.11.2 Asynchronous Protocols...................................................................... 7-134 7.10.12 Digital Phase-Locked Loop (DPLL) ..................................................... 7-135 7.10.12.1 Data Encoding..................................................................................... 7-135 7.10.12.2 DPLL Operation................................................................................... 7-136 7.10.13 Clock Glitch Detection ......................................................................... 7-139 7.10.14 Disabling the SCCs on the Fly ............................................................ 7-139 7.10.14.1 SCC Transmitter Full Sequence.......................................................... 7-140 7 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 7.10.17.6 HDLC Command Set ...........................................................................7-175 7.10.17.6.1 Transmit Commands............................................................................7-175 7.10.17.6.2 Receive Commands.............................................................................7-176 7.10.17.7 HDLC Error-handling Procedure..........................................................7-176 7.10.17.7.1 Transmission Errors.............................................................................7-176 7.10.17.7.2 Reception Errors ..................................................................................7-177 7.10.17.8 HDLC Mode Register (PSMR) .............................................................7-178 7.10.17.9 HDLC Receive Buffer Descriptor (Rx BD) ...........................................7-179 7 ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.10.20.9 Transmitting and Receiving the Synchronization Sequence ............... 7-208 7.10.20.10 BISYNC Error-Handling PROCEDURE............................................... 7-209 7.10.20.10.1 Transmission Errors ............................................................................ 7-209 7.10.20.10.2 Reception Errors ................................................................................. 7-209 7.10.20.11 BISYNC Mode Register (PSMR)......................................................... 7-209 7.10.20.12 BISYNC Receive Buffer Descriptor (Rx BD) ....................................... 7-211 7.10.20.13 BISYNC Transmit Buffer Descriptor (Tx BD)....................................... 7-213 7 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 7.10.23.10.1 Transmit Commands............................................................................7-250 7.10.23.10.2 Receive Commands.............................................................................7-251 7.10.23.10.3 SET GROUP ADDRESS Command....................................................7-251 7.10.23.11 Ethernet Address Recognition .............................................................7-252 7.10.23.12 Hash Table Algorithm ..........................................................................7-253 7.10.23.13 Interpacket Gap Time ..........................................................................7-254 7.10.23.14 Collision Handling ................................................................................7-254 7.10.23.15 Internal and External Loopback ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.11.7.7.2 Receive Commands ............................................................................ 7-280 7.11.7.8 Send Break (Transmitter) .................................................................... 7-280 7.11.7.9 Sending a Preamble (Transmitter) ...................................................... 7-280 7.11.7.10 SMC UART Error-Handling Procedure................................................ 7-281 7.11.7.10.1 Overrun Error ...................................................................................... 7-281 7.11.7.10.2 Parity Error .......................................................................................... 7-281 7.11.7.10.3 Idle Sequence Receive ....................................................................... 7-281 7.11.7.10.4 Framing Error ...................................................................................... 7-281 7 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 7.11.14.3 SMC Commands in GCI Mode ............................................................7-307 7.11.14.4 SMC GCI Mode Register (SMCMR) ....................................................7-308 7.11.14.5 SMC Monitor Channel Rx BD ..............................................................7-309 7.11.14.6 SMC Monitor Channel Tx BD...............................................................7-310 7.11.14.7 SMC C/I Channel Receive Buffer Descriptor (Rx BD) .........................7-310 7 ...
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... Freescale Semiconductor, Inc. Paragraph Number 7.13.5.2 Pulsed Handshake Timing .................................................................. 7-336 7.13.6 Transparent Data Transfers ................................................................ 7-338 7.13.7 Programming Model ............................................................................ 7-338 7.13.7.1 Parameter RAM................................................................................... 7-338 7.13.7.2 PIP Configuration Register (PIPC) ...................................................... 7-339 7.13.7.3 PIP Timing Parameters Register (PTPR)............................................ 7-341 7.13.7.4 PIP Buffer Descriptors......................................................................... 7-341 7 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 7.13.9.1 Port B Assignment Registers (PBPAR) ...............................................7-356 7.13.9.2 Data Direction Register (PBDIR) .........................................................7-356 7.13.9.3 Data Register (PBDAT)........................................................................7-356 7.13.9.4 Open-Drain Register (PBODR)............................................................7-356 7.14 Parallel I/O Ports..................................................................................7-356 7.14.1 Parallel I/O Key Features.....................................................................7-357 7.14.2 Parallel I/O Overview ...
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... Freescale Semiconductor, Inc. Paragraph Number 8.1 Overview ................................................................................................. 8-1 8.2 TAP Controller......................................................................................... 8-2 8.3 Boundary Scan Register ......................................................................... 8-3 8.4 Instruction Register ............................................................................... 8-10 8.4.1 EXTEST ................................................................................................ 8-10 8.4.2 SAMPLE/PRELOAD.............................................................................. 8-10 8.4.3 BYPASS ................................................................................................ 8-11 8.4.4 CLAMP .................................................................................................. 8-11 8.4.5 HI-Z ....................................................................................................... 8-11 8.5 QUICC Restrictions ............................................................................... 8-11 8.6 Non-Scan Chain Operation ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number Step 4: Write the MBAR.........................................................................9-14 Step 5: Verify a Dual-Port RAM Location...............................................9-14 Step 6: Is This a Power-Up Reset?........................................................9-14 Step 7: Deal with the Clock Synthesizer ................................................9-14 Step 8: Initialize System Protection .......................................................9-15 Step 9: Clear Entire Dual-Port RAM ......................................................9-15 Step 10: Write the PEPAR ...
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... Freescale Semiconductor, Inc. Paragraph Number 9.4.2.7 EEPROM............................................................................................... 9-45 9.4.2.8 DRAM SIMM ......................................................................................... 9-45 9.4.2.9 DRAM Devices. ..................................................................................... 9-46 9.4.3 Software Configuration.......................................................................... 9-48 9.4.3.1 Basic Initialization.................................................................................. 9-49 9.4.3.2 Configuring the Memory Controller. ...................................................... 9-49 9.4.4 Interfacing Multiple QUICCs to an MC68EC040 ................................... 9-51 9.5 Selecting Cache Modes on the MC68EC040........................................ 9-51 9 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number 9.8.1.11 MC68EC030 Caching Configuration......................................................9-79 9.8.1.12 Double Bus Fault ...................................................................................9-79 9.8.1.13 JTAG and Three-State...........................................................................9-79 9.8.1.14 QUICC Serial Ports................................................................................9-79 9.8.2 Memory Interfaces .................................................................................9-79 9.8.2.1 QUICC Memory Interface Pins ..............................................................9-80 9.8.2.2 Regular EPROM or Flash EPROM ........................................................9-80 9 ...
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... Freescale Semiconductor, Inc. Paragraph Number 10.20 Interrupt Controller AC Electrical Specifications.................................. 10-66 10.21 Baud Rate Generator AC Electrical Specifications ............................. 10-67 10.22 Timer Electrical Specifications ............................................................ 10-68 10.23 SI Electrical Specifications .................................................................. 10-69 10.24 SCC in NMSI Mode—External Clock Electrical Specifications .......... 10-75 10.25 SCC in NMSI MODE—Internal Clock Electrical Specifications.......... 10-75 10 ...
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... Freescale Semiconductor, Inc. Table of Contents Paragraph Number C.4 Asynchronous HDLC for PPP ................................................................. C-6 C.4.1 Key Features........................................................................................... C-6 C.4.2 Performance ........................................................................................... C-7 C.5 PROFIBUS Controller ............................................................................. C-7 C.5.1 Key Features........................................................................................... C-7 C.6 Enhanced Ethernet Filtering ................................................................... C-8 C.6.1 Key Features........................................................................................... C-8 C.6.2 Performance ........................................................................................... C-8 D.1 QUICC32 Key Features ...
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... Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION The MC68360 QUad Integrated Communication Controller (QUICC chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications activities. The QUICC (pro- nounced “quick”) can be described as a next-generation MC68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term " ...
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... Freescale Semiconductor, Inc. Introduction —Glueless Interface to DRAM Single In-Line Memory Modules (SIMMs), Static Ran- dom-Access Memory (SRAM), Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc. —Four CAS lines, Four WE lines, One OE line —Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory) — ...
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... Freescale Semiconductor, Inc. —Independent (Can Be Connected to Any SCC or SMC) —Allows Changes During Operation —Autobaud Support Option • Four SCCs —Ethernet/IEEE 802.3 Optional on SCC1 (Full 10-Mbps Support) 1 —HDLC/SDLC (All Four Channels Supported at 2 Mbps) —HDLC Bus (Implements an HDLC-Based Local Area Network (LAN)) 2 — ...
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... Freescale Semiconductor, Inc. Introduction • Parallel Interface Port 4 —Centronics Interface Support —Supports Fast Connection Between QUICCs • 240 Pins Defined: 241-Lead Pin Grid Array (PGA) and 240-Lead Plastic Quad Flat Pack (PQFP) 1.2 QUICC ARCHITECTURE OVERVIEW The QUICC is 32-bit controller that is an extension of other members of the Motorola M68300 family ...
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... Freescale Semiconductor, Inc. 1.2.1 CPU32+ Core The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path and 32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate on 32-bit external operands with one bus cycle ...
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... Freescale Semiconductor, Inc. Introduction 1.2.3 Communications Processor Module (CPM) The CPM contains features that allow the QUICC to excel in communications and control applications. These features may be divided into three sub-groups: • Communications Processor (CP) • Two IDMA Controllers • Four General-Purpose Timers The CP provides the communication features of the QUICC. Included are a RISC processor, four SCCs, two SMCs, one SPI, 2 ...
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... Freescale Semiconductor, Inc. Because of the similarity of the QUICC SIM60 and CPU to other members of the M68300 family, such as the MC68332 and the MC68340, previous users of these devices will be comfortable with these same features on the QUICC. 1.3.2 Hardware Compatibility Issues The following list summarizes the hardware differences between the MC68302 and the QUICC: • ...
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... Freescale Semiconductor, Inc. Introduction mand registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register names and usage are retained. More importantly, the basic structure of a buffer descriptor (BD) on the QUICC is identical to that of the MC68302, except for a few new bit functions that were added. (In a few cases, a bit status word had to be shifted.) • ...
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... Freescale Semiconductor, Inc. QUICC MC68360 CS0 OE WE0 DATA ADDRESS CS7 WE3–WE0 RAS2 RAS1 CAS3–CAS0 R/W PRTY3–PRTY0 Figure 1-3. Larger QUICC System Configuration 1.5 QUICC SERIAL CONFIGURATIONS The QUICC offers an extremely flexible set of communications capabilities. Although a full understanding of the possibilities requires reading the appropriate sections, some of the possibilities are shown in the following diagrams ...
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... Freescale Semiconductor, Inc. Introduction connections to the attachment unit interface (AUI) or twisted-pair Ethernet formats and pro- vides a glueless interface to the QUICC. Figure 1-4. Ethernet LAN Capability Figure 1-5 shows the AppleTalk LAN capability of the QUICC. Note that the MC68302 requires an extra device, the MC68195 LocalTalk adapter, to interface to AppleTalk. ...
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... Freescale Semiconductor, Inc. Figure 1-7 shows the original SDLC application, which can be implemented by both QUICCs and MC68302s. Figure 1-7. FSDLC Bus Implementation Figure 1-8 shows a UART LAN configuration that is supported by both the QUICC and the MC68302, as well as many other industry UARTs. ...
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... Freescale Semiconductor, Inc. Introduction Figure 1-8. UART LAN Implementation Figure 1-9 shows how the SPIs on the QUICC can be used to connect devices together into a local bus. The SPI exists on many other Motorola devices, such as the MC68HC11 micro- controller, and a number of peripherals such as A/D and D/A converters, LED drivers, LCD drivers, real-time clocks, serial EEPROM, PLL frequency synthesizers, and shift registers ...
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... Freescale Semiconductor, Inc. Figure 1-10 shows how the SCP on the MC68302 can be used to interface to the QUICC SPI. MC68302 MASTER NOTE: The MC68302 SCP can communicate with the QUICC SPI. Figure 1-10. SPI Implementation Using SCP Figure 1-11 shows how the SPI on the QUICC can interface to another QUICC or SPI-based peripherals ...
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... Freescale Semiconductor, Inc. Introduction Figure 1-13 shows how the PIP can also be used to implement a fast parallel connection between devices. QUICC NOTE: Fast parallel connection between QUICCs. Figure 1-13. Fast Parallel Connection Implementation Figure 1-14 shows which SCC protocols may be used to connect SCCs on the QUICC and the MC68302 ...
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... Freescale Semiconductor, Inc. QUICC QUICC QUICC Figure 1-16. Other Point-to-Point Implementations Figure 1-17 shows how up to six of the serial channels can connect to a TDM interface. The QUICC provides a built-in time-slot assigner for access to the TDM time slots. Other chan- nels can work with their own set of pins, allowing possibilities like an Ethernet to T1 bridge, etc ...
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... Freescale Semiconductor, Inc. Introduction ANY COMBINATION OF SCCs NOTE: Two TDM buses may be simultaneously supported Figure 1-18. Dual TDM Bus Implementation 1.6 QUICC SERIAL CONFIGURATION EXAMPLES Figure 1-19 shows a situation where multiple QUICCs can communicate over a TDM line. This can be used, for instance, to implement an 8-channel line card. The SCCs implement the line interfaces, and the SMCs provide the local on-board communication between the QUICCs ...
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... Freescale Semiconductor, Inc. Figure 1-20 shows a general-purpose application that includes Ethernet, AppleTalk, an HDLC connection line, an HDLC connection to frame relay, a UART debug monitor port, a totally transparent data stream port, and an SPI connection to a serial EEPROM. SYSTEM BUS SERIAL SPI EEPROM UART SMC2 ...
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... Freescale Semiconductor, Inc. Introduction The QUICC has special features in slave mode to support the M68040 family. When the QUICC is used in this way said MC68040 companion mode. Figure 1-22 shows how a QUICC in slave mode can interface to a MC68EC040. (The MC68EC040 is a low- cost version of the MC68040 with identical integer performance, but without the memory management unit (MMU) and the floating-point unit (FPU) ...
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... Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the QUICC input and output signals in their func- tional groups as shown in Figure 2-1. 2.1 SYSTEM BUS SIGNAL INDEX The QUICC system bus signals consist of two groups. The first group, listed in Table 2-1, consists of system bus signals that exist when the QUICC is in the normal mode (CPU32+ enabled) ...
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... Freescale Semiconductor, Inc. Signal Descriptions Write enable does not have the capability to follow dynamic bus sizing with external assertion of DSACK. Write enable will al- ways follow the port size that is programed in GMR and the OR. For more information see 6.10 Memory Controller. RXD1/PA0 ...
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... Freescale Semiconductor, Inc. Table 2-1. System Bus Signal Index (Normal Operation) Group Signal Name Address Address Bus Address Bus/Byte Write Enables Function Codes Data Data Bus 31–16 Data Bus 15–0 Parity Parity 2–0 Parity3/16BM Parity Error Chip Select/Row Ad- Memory dress Select 7/ ...
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... Freescale Semiconductor, Inc. Signal Descriptions Table 2-1. System Bus Signal Index (Normal Operation)(Continued) Group Signal Name System Soft Reset Control Hard Reset Halt Bus Error Clock and Test System Clock Out 1 System Clock Out 2 Crystal Oscillator External Filter Ca- pacitor Clock Mode Select 1– ...
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... Freescale Semiconductor, Inc. 2.1.2 Function Codes (FC3–FC0) These three-state bidirectional signals identify the processor state and the address space of the current bus cycle as noted in Table 2-2. The function code pins provide the purpose of each bus cycle to external logic. Other bus masters besides the QUICC may also output function codes during their bus cycles ...
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... Freescale Semiconductor, Inc. Signal Descriptions pins are the only data pins used. Refer to Section 4 Bus Operation for information on the data bus and its relationship to bus operation. 2.1.3.2 DATA BUS (D15–D0). These pins can function as 16 additional data pins used in long-word and 3-byte transfers. They are three-stated and not used if the QUICC is config- ured into 16-bit bus mode ...
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... Freescale Semiconductor, Inc. RAS7/CS7—Row address select 7 or chip select 7 output signal. IACK7—The QUICC asserts this pin to indicate a level 7 external interrupt during an inter- rupt acknowledge cycle. Peripherals can use the IACKx strobes instead of monitoring the address bus and function codes to determine that an interrupt acknowledge cycle is in progress and to obtain the current interrupt level ...
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... Freescale Semiconductor, Inc. Signal Descriptions 2.1.7.1 DATA AND SIZE ACKNOWLEDGE (DSACK1–DSACK0). These two active-low bidirectional signals allow asynchronous data transfers and dynamic data bus sizing between the QUICC and external devices (see Table 2-3). DSACK1 1 (Negated) 1 (Negated) 1 (Negated) 0 (Asserted) 0 (Asserted) ...
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... Freescale Semiconductor, Inc. 2.1.7.7 OUTPUT ENABLE/ADDRESS MULTIPLEX (OE/AMUX). This pin can be pro- grammed as the output enable (OE) output or as the address multiplex output. OE—During a read cycle, this output signal is driven by the bus master to indicate that an external device should place valid data on the data bus. OE may used to save an external inversion of the R/W signal. AMUX— ...
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... Freescale Semiconductor, Inc. Signal Descriptions BCLRO—This active-low open-drain output indicates that one of the QUICC internal bus masters is requesting the external bus master to release the bus. CONFIG1—See 2.1.13 Initial Configuration Pins (CONFIG) for the description. RAS2—See 2.1.5.1 Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) for the description ...
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... Freescale Semiconductor, Inc. is the general system clock. CLKO2 is 2 CLKO1 if the on-chip clock synthesizer PLL is used, and is 1 CLKO1 otherwise. 2.1.10.2 CRYSTAL OSCILLATOR (EXTAL, XTAL). These two pins are the connections for an external crystal to the internal oscillator circuit external oscillator is used, it should be connected to EXTAL, with XTAL left open ...
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... Freescale Semiconductor, Inc. Signal Descriptions signal is the serial clock used to transfer commands/status to and from the CPU32+ during background debug mode. 2.1.11.5 FREEZE/INITIAL CONFIGURATION (FREEZE/CONFIG2). This pin can be pro- grammed as the freeze output or as the initial configuration pin 2 input signal during system reset. FREEZE— ...
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... Freescale Semiconductor, Inc. Table 2-6. Initial Configuration Configuration Pins CONFIG2/ CONFIG1/ CONFIG0/ FREEZE BCLRO RMC All CONFIG pins do have an internal pull-up resistor during re- set configuration other than the default (CONFIG2-1 = 111) is desired, these pins should be driven by an active open collec- tor device during the assertion of RESETH. ...
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... Freescale Semiconductor, Inc. Signal Descriptions 2.2 SYSTEM BUS SIGNAL INDEX IN SLAVE MODE The CONFIG2–CONFIG0 pins are used to cause the QUICC to enter the slave mode. The signal name, mnemonic, and a brief functional description are presented in Table 2-7. The rest of the QUICC pins maintain their functionality in slave mode. See Section 4 Bus Oper- ation for details ...
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... Freescale Semiconductor, Inc. Table 2-7. System Bus Signal Index (Slave Mode) (Continued) Master Mode Slave Mode Mnemonic Signal Name Parity 0/Interrupt Out- PRTY0 put 2 Parity 1/Interrupt Out- PRTY1 put 1 Parity 2/ PRTY2 Interrupt Output 0/ Request Output AVEC/IACK5 Autovector Output Bus Clear Input/ ...
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... Freescale Semiconductor, Inc. Signal Descriptions Table 2-8. Peripherals Signal Index (Continued) Group Signal Name Mnemonic Timer Output TOUT4–TOUT1 SPI Master-In Slave- SPI SPIMISO Out SPI Master-Out SPIMOSI Slave-In SPI Clock SPICLK SPI Select SPISEL SMC SMC Receive Data SMRXD2–SMRXD1 Serial data input to the SMCs. (I) SMC Transmit Data SMTXD2– ...
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... Freescale Semiconductor, Inc. Signal Descriptions 2-17 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Signal Descriptions 2-18 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. SECTION 3 QUICC MEMORY MAP The following tables present a programmer’s model (register map) of all registers in the QUICC. For more information about a particular register, refer to the description for the mod- ule or sub-module indicated in the right column. The address column indicates the offset of the register from the address stored in the module base address register (MBAR) ...
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... Freescale Semiconductor, Inc. QUICC Memory Map 4KB 4KB Figure 3-1. QUICC Memory Map 3.1 DUAL-PORT RAM MEMORY MAP The internal 2816-byte (2560-byte on REV A and B mask) dual-port RAM is partitioned to 1792 bytes (1536 bytes on REV A and B mask) of system RAM, 256-byte microcode scratch area, and 768 bytes of parameter RAM (see Table 3-1). Its base address, called dual-port RAM base (DPRBASE), is the address pointed to by the MBAR ...
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... Freescale Semiconductor, Inc. The parameter RAM contains the protocol-specific parameters. For detailed information about the use of the buffer descriptors and protocol parameters in a specific protocol, see Section 7 Communication Processor Module (CPM). Address DPRBASE + 0 DPRBASE + 3FF DPRBASE + 400 DPRBASE + 5FF DPRBASE + 600 ...
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... Freescale Semiconductor, Inc. QUICC Memory Map Table 3-2. CPM Sub-Module Base Addresses 3.3 INTERNAL REGISTERS MEMORY MAP In addition to the internal dual-port RAM, there are a number of internal registers to support the functions of the various CPU32+ core peripherals. The internal registers (see Table 3-3 and Table 3-4) are memory-mapped registers offset from the register base (REGBASE) pointer ...
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... Freescale Semiconductor, Inc. Table 3-3. QUICC SIM Registers Memory Map Address Name Width REGB + 0000 MCR 32 REGB + 0004 32 REGB + 0008 AVR 8 REGB + 0009 RSR 8 REGB + 000a 16 REGB + 000c CLKOCR 8 REGB + 000d REGB + 0010 PLLCR 16 REGB + 0012 16 REGB + 0014 CDVCR 16 REGB + 0016 ...
Page 72
... Freescale Semiconductor, Inc. QUICC Memory Map Table 3-3. QUICC SIM Registers Memory Map REGB + 0078 to REGB + 007f REGB + 0080 BR3 32 REGB + 0084 OR3 32 REGB + 0088 to REGB + 008f REGB + 0090 BR4 32 REGB + 0094 OR4 32 REGB + 0098 to REGB + 009f REGB + 00a0 BR5 32 REGB + 00a4 ...
Page 73
... Freescale Semiconductor, Inc. Table 3-4. QUICC CPM Registers Memory Map REGB + 515 8 REGB + 516 CMAR1 8 REGB + 517 8 REGB + 518 CSR1 8 REGB + 519 24 REGB + 51C SDSR 8 REGB + 51D 8 REGB + 51E SDCR 16 REGB + 520 SDAR 32 REGB + 524 16 REGB + 526 CMR2 16 REGB + 528 SAPR2 ...
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... Freescale Semiconductor, Inc. QUICC Memory Map Table 3-4. QUICC CPM Registers Memory Map REGB + 582 to REGB + 58f REGB + 590 TMR1 16 REGB + 592 TMR2 16 REGB + 594 TRR1 16 REGB + 596 TRR2 16 REGB + 598 TCR1 16 REGB + 59A TCR2 16 REGB + 59C TCN1 16 REGB + 59E TCN2 ...
Page 75
... Freescale Semiconductor, Inc. Table 3-4. QUICC CPM Registers Memory Map REGB + 60e DSR1 16 REGB + 610 SCCE1 16 REGB + 614 SCCM1 16 REGB + 617 SCCS1 8 REGB + 618 to REGB + 61f REGB + 620 GSMR_L2 32 REGB + 624 GSMR_H2 32 REGB + 628 PSMR2 16 REGB + 62c TODR2 16 REGB + 62e DSR2 ...
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... Freescale Semiconductor, Inc. QUICC Memory Map Table 3-4. QUICC CPM Registers Memory Map REGB + 692 SMCMR2 16 REGB + 696 SMCE2 8 REGB + 69a SMCM2 8 REGB + 69C REGB + 6A0 SPMODE 16 REGB + 6A6 SPIE 8 REGB + 6AA SPIM 8 REGB + 6AD SPCOM 8 REGB + 6B2 PIPC 16 REGB + 6B6 ...
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... Freescale Semiconductor, Inc. SECTION 4 BUS OPERATION This section provides a functional description of the system bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the QUICC or an external device is the bus master ...
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... Freescale Semiconductor, Inc. Bus Operation aligned on word or long-word boundaries, respectively. The QUICC IDMAs, when used, reduce the misalignment overhead to a minimum. 4.1 BUS TRANSFER SIGNALS The bus transfers information between the QUICC and external memory or a peripheral device. External devices can accept or provide 8, 16 bits in parallel and must follow the handshake protocol described in this section ...
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... Freescale Semiconductor, Inc. 4.1.1 Bus Control Signals The QUICC initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with the FC signals. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles) ...
Page 80
... Freescale Semiconductor, Inc. Bus Operation 4.1.3 Address Bus (A31–A0) The address bus signals are outputs that define the address of the byte (or the most signif- icant byte transferred during a bus cycle. The QUICC places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. ...
Page 81
... Freescale Semiconductor, Inc. The equations of the byte write enables for 32-bit port (16BM = 1) are as follows: WE0 = R WE1 = R not {(A1 * SIZ0) + (A0 * A1) + (A1 * SIZ1)} WE2 = R not {(A0 * A1) + (A1 * SIZ0 * SIZ1) + (A1 * SIZ0 * SIZ1 SIZ0)} WE3 = R not {(A0 * SIZ0 * SIZ1) + (SIZ0 * SIZ1) + (A0 * A1) + (A1 * SIZ1)} These signals have the same timing as AS. The equations are valid only for a 32-bit port. ...
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... Freescale Semiconductor, Inc. Bus Operation appropriate timing described in this section and in Section 10 Electrical Characteristics. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 4.5 Bus Exception Control Cycles for additional information on the use of these signals. See the memory controller description in Section 6 System Integration Module (SIM60) for precautions about asserting BERR externally too early during DRAM and SRAM cycles con- trolled by the memory controller ...
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... Freescale Semiconductor, Inc. the port width. For instance, a 32-bit device always returns DSACKx for a 32-bit port (regard- less of whether the bus cycle is a byte, word, or long-word operation). Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on data bus bits 0– ...
Page 84
... Freescale Semiconductor, Inc. Bus Operation 0P0 0 REGISTER MULTIPLEXER EXTERNAL D31–D24 DATA BUS ADDRESS BYTE 0 xxxxxxxx0 INCREASING MEMORY ADDRESSES xxxxxxxx0 BYTE 0 2 BYTE 2 xxxxxxxx0 BYTE 0 1 BYTE 1 2 BYTE 2 BYTE 3 3 Figure 4-3. QUICC Interface to Various Port Sizes The SIZ0 and SIZ1 outputs indicate the remaining number of bytes to be transferred during the current bus cycle (see Table 4-3) ...
Page 85
... Freescale Semiconductor, Inc. Table 4-4. Address Offset Encoding Table 4-5 lists the bytes required on the data bus for read cycles. The entries shown as OPx are portions of the requested operand that are read during that bus cycle and are defined by SIZ0, SIZ1, A0, and A1 for the bus cycle. Bytes labeled x are “don’t cares” and are not required during that read cycle ...
Page 86
... Freescale Semiconductor, Inc. Bus Operation 16 bits. SIZ0 and SIZ1 indicate that a word remains to be transferred; A0 and A1 indicate that the word corresponds to an offset of two from the base address. The multiplexer follows the pattern corresponding to this configuration of the size and address signals and places the two least significant bytes of the long word on the word portion of the bus (D16– ...
Page 87
... Freescale Semiconductor, Inc. S0 CLKO1 A31– FC3–FC0 SIZ1 SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 Figure 4-5. Long-Word Operand Write Timing (16-Bit Data Port) Figure 4-6 shows a word transfer to an 8-bit bus port. Like the preceding example, this example requires two bus cycles. Each bus cycle transfers a single byte. The size signals for the first cycle specify two bytes ...
Page 88
... Freescale Semiconductor, Inc. Bus Operation that are misaligned. For maximum performance, data items should be aligned on their nat- ural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception. 15 WORD OPERAND ...
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... Freescale Semiconductor, Inc. CLKO1 A31– FC3–FC0 SIZ1 SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 Figure 4-7. Word Operand Write Timing (8-Bit Data Port) Figure 4-8 shows the transfer of a long-word operand to an odd address in word-organized memory, which requires three bus cycles. For the first cycle, the SIZx signals specify a long- word transfer, and the address offset (A2– ...
Page 90
... Freescale Semiconductor, Inc. Bus Operation 31 0P0 DATA BUS D31 WORD MEMORY MSB 0P0 XXX 0P1 0P2 OP3 XXX Figure 4-8. Misaligned Long-Word Transfer to Word Port Example 4-14 For More Information On This Product, LONG-WORD OPERAND 0P1 0P2 0P3 D16 MC68360 LSB SIZ1 ...
Page 91
... Freescale Semiconductor, Inc CLKO1 A31– FC3–FC0 SIZ1 SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE Figure 4-9. Misaligned Long-Word Transfer to Word Port Timing Figure 4-10 and Figure 4-11 show a word transfer to an odd address in word-organized memory ...
Page 92
... Freescale Semiconductor, Inc. Bus Operation WORD OPERAND 15 OP2 D31 DATA BUS WORD MEMORY MSB XXX 0P3 Figure 4-10. Misaligned Word Transfer to Word Port Example 4-16 For More Information On This Product, 0 OP3 D16 MC68360 SIZ1 SIZ0 LSB 0P2 XXX MC68360 USER’S MANUAL Go to: www ...
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... Freescale Semiconductor, Inc. S0 CLKO1 A31– FC3–FC0 SIZ1 SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 Figure 4-11. Misaligned Word Transfer to Word Port Timing Figure 4-12 and Figure 4-13 show an example of a long-word transfer to an odd address in long-word-organized memory. In this example, a long-word access is attempted beginning at the least significant byte of a long-word-organized memory ...
Page 94
... Freescale Semiconductor, Inc. Bus Operation LONG-WORD OPERAND 15 0P0 0P1 D31 DATA BUS LONG-WORD MEMORY MSB UMB XXX XXX 0P1 0P2 Figure 4-12. Misaligned Long-Word Transfer to Long-Word Port Example 4-18 For More Information On This Product, 0 0P2 0P3 D0 MC68EC030 LMB LSB SIZ1 SIZ0 ...
Page 95
... Freescale Semiconductor, Inc. S0 CLKO1 A31– FC2–FC0 SIZ1 SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 Figure 4-13. Misaligned Long-Word Transfer to Long-Word Port Timing 4.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment The combination of operand size, operand alignment, and port size determines the number of bus cycles required to perform a particular memory access ...
Page 96
... Freescale Semiconductor, Inc. Bus Operation Table 4-7. Memory Alignment and Port Size Influence A1–A0 Instruction 1 Byte Operand Word Operand Long-Word Operand Notes: 1. Data Port Size—32 Bits:16 Bits:8 Bits 2. Instruction reads can either be two words from an even-word boundary, or one word from an odd-word boundary. ...
Page 97
... Freescale Semiconductor, Inc. asserted in any asynchronous system. If this maximum delay time is violated, the QUICC may exhibit erratic behavior. 4.2.5 Synchronous Operation with DSACKx Although cycles terminated with DSACKx are classified as asynchronous, cycles terminated with DSACKx can also operate synchronously in that signals are interpreted relative to clock edges ...
Page 98
... Freescale Semiconductor, Inc. Bus Operation S0 S1 CLKO1 AS DS R/W DSACKx D31–D0 TWO WAIT STATES IN READ * DSACKx only internally asserted for fast termination cycles. Figure 4-14. Fast Termination Timing When using the fast termination option (cycle length is two clocks asserted only in a read cycle, not in a write cycle. ...
Page 99
... Freescale Semiconductor, Inc. 4.3.1 Read Cycle During a read cycle, the QUICC receives data from a memory or peripheral device. If the instruction specifies a long-word operation, the QUICC attempts to read four bytes at once. For a word operation, the QUICC attempts to read two bytes at once. For a byte operation, the QUICC reads one byte ...
Page 100
... Freescale Semiconductor, Inc. Bus Operation S0 S2 CLKO1 A31– FC3–FC0 SIZ1 WORD SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 WORD READ Figure 4-17. Byte and Word Read Cycles—32-Bit Port Timing 4-24 For More Information On This Product, ...
Page 101
... Freescale Semiconductor, Inc CLKO1 A31– FC3–FC0 SIZ1 LONG WORD SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 WORD READ LONG-WORD OPERAND READ FROM 16-BIT PORT Figure 4-18. Long-Word Read—16-Bit and 32-Bit Port Timing State 0—The read cycle starts in state 0 (S0). During S0, the QUICC places a valid address on A31– ...
Page 102
... Freescale Semiconductor, Inc. Bus Operation State 1—One-half clock later, in state 1 (S1), the QUICC asserts AS indicating a valid address on the address bus. The QUICC also asserts DS and OE during S1. The selected device uses R/W, SIZ1 or SIZ0, A0, A1, DS, and OE to place its information on the data bus. ...
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... Freescale Semiconductor, Inc CLKO1 A31– FC3–FC0 SIZ1 LONG WORD SIZ0 R DSACK1 DSACK0 D31–D0 READ NOTE: WE3–WE0 is not shown. Figure 4-20. Read-Write-Read Cycles—32-Bit Port State 0—The write cycle starts in S0. During S0, the QUICC places a valid address on A31– ...
Page 104
... Freescale Semiconductor, Inc. Bus Operation State 3—The QUICC asserts DS during S3, indicating that data is stable on the data bus. As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACKx is not recognized by the start of S3, the QUICC inserts wait states instead of pro- ceeding to S4 and S5 ...
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... Freescale Semiconductor, Inc. S0 CLK O1 A31–A0 FC3–FC0 SIZ1–SIZ0 R/W RMC AS DS DSACKx D31–D0 NOTE: OE and WE3–WE0 are not shown. Figure 4-21. Read-Modify-Write Cycle Timing State 0—The QUICC asserts RMC identify a read-modify-write cycle. The QUICC places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the operation ...
Page 106
... Freescale Semiconductor, Inc. Bus Operation nous input setup and hold times around the end of S2. If wait states are added, the QUICC continues to sample DSACKx on the falling edges of the clock until one is recognized. State 4—At the end of S4, the QUICC latches the incoming data. ...
Page 107
... Freescale Semiconductor, Inc. negate DSACKx within approximately one clock period after sensing the negation DS. 4.4 CPU SPACE CYCLES FC2–FC0 select user and supervisor program and data areas. The area selected by function code FC3–FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP broadcast, module base address register access, and interrupt acknowledge cycles described in the following paragraphs use CPU space ...
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... Freescale Semiconductor, Inc. Bus Operation When the CPU32+ acknowledges hardware breakpoint (BKPT pin assertion or internal breakpoint logic) with background mode disabled, the CPU32+ performs a word read from CPU space, type address corresponding to all ones on A4–A2 (BKPT#7), and the T-bit (A1) is set. If this bus cycle is terminated by BERR, the QUICC performs hardware breakpoint exception processing ...
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... Freescale Semiconductor, Inc. PROCESSOR BREAKPOINT ACKNOWLEDGE IF BREAKPOINT INSTRUCTION EXECUTED: 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON A19–A16 4) PLACE BREAKPOINT NUMBER ON A4–A2 5) CLEAR T-BIT (A1) 6) SET SIZx TO WORD 7) ASSERT AS AND DS IF BKPT PIN OR INTERNAL LOGIC ASSERTED BKPT ...
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... Freescale Semiconductor, Inc. Bus Operation CLKO1 A31–A20 A19–A16 A4–A1 A15–A5, A0 FC3–FC0 SIZ0 SIZ1 AS DS R/W DSACKx D23–D16 D31–D24 BERR HALT BKPT BREAKPOINT OCCURS Figure 4-24. Breakpoint Acknowledge Cycle Timing (Opcode Returned) 4-34 For More Information On This Product, ...
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... Freescale Semiconductor, Inc CLKO1 A31–A20 A19–A16 A4–A1 A15–A5, A0 FC3–FC0 SIZ0 SIZ1 AS DS R/W DSACKx D23–D16 D31–D24 BERR HALT BKPT BREAKPOINT OCCURS Figure 4-25. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 4.4.2 LPSTOP Broadcast Cycle The LPSTOP broadcast cycle is generated by the CPU32+ executing the LPSTOP instruc- tion ...
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... Freescale Semiconductor, Inc. Bus Operation so the CPU32+ performs a CPU space type 3 write with the interrupt mask level (I2–I0) encoded on bits 2–0 of the data bus, as shown in the following figure. The CPU space type 3 cycle waits for the bus to be available, and is shown externally to indicate to external devices that the QUICC is going into LPSTOP mode ...
Page 113
... Freescale Semiconductor, Inc. The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 4.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows: 1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space. ...
Page 114
... Freescale Semiconductor, Inc. Bus Operation S0 S2 CLKO1 A31–A4 A3–A1 A0 FC3–FC0 SIZ0 SIZ1 R DSACKx D23–D16 D31–D24 IRQ7–IRQ1 IACK7–IACK1 READ CYCLE * Internal arbitration may take between 0–2 clock cycles. Figure 4-27. Interrupt Acknowledge Cycle Timing 4.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector) ...
Page 115
... Freescale Semiconductor, Inc. during an interrupt acknowledge cycle terminated by AVEC. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When the AVEC signal is asserted instead of DSACKx during an interrupt acknowledge cycle, the QUICC ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)) ...
Page 116
... Freescale Semiconductor, Inc. Bus Operation S0 S2 CLKO1 A31–A4 A3–A1 A0 FC3–FC0 SIZ0 SIZ1 R DSACKx D31–D0 AVEC IRQ7–IRQ1 IACK7–IACK1 READ CYCLE * Internal Arbitration may take between 0–2 clock cycles. Figure 4-28. Autovector Operation Timing 4.4.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or exter- nal, are arbitrated internally ...
Page 117
... Freescale Semiconductor, Inc. interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition. The QUICC automatically generates the spurious interrupt vector number, 24, instead of the interrupt vector number in this case. When an external device does not respond to an interrupt acknowledge cycle with AVEC or DSACKx, a bus monitor must assert BERR, which results in the CPU32+ taking the spurious interrupt vector ...
Page 118
... Freescale Semiconductor, Inc. Bus Operation EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3). EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACKx until data is verified and assert BERR and HALT simultaneously to in- dicate to the QUICC to automatically retry the error cycle (case 5), or, if data is valid, assert DSACKx (case 1) ...
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... Freescale Semiconductor, Inc. able operation of the QUICC. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the QUICC may enter exception processing immediately following the bus cycle may defer pro- cessing the exception ...
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... Freescale Semiconductor, Inc. Bus Operation S0 CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D0 BERR Figure 4-30. Late Bus Error with DSACKx In the second case, in which BERR is asserted after DSACKx is asserted, BERR must be asserted within the time specified for purely asynchronous operation must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACKx is recognized ...
Page 121
... Freescale Semiconductor, Inc CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D0 BERR HALT READ CYCLE WITH The QUICC retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR at the same time as BERR and HALT provides a relinquish and retry opera- tion ...
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... Freescale Semiconductor, Inc. Bus Operation tire word access will be retried. This is true even if the relinquish and retry was asserted on the second access and the first 8-bit access was completed normally CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D10 BERR HALT Figure 4-32. Late Retry Sequence 4 ...
Page 123
... Freescale Semiconductor, Inc. When the QUICC completes a bus cycle with HALT asserted, D31–D0 is placed in the high- impedance state, and bus control signals are driven inactive (not high-impedance state); the address, function code, size, and read/write signals remain in the same state. The halt oper- ation has no effect on bus arbitration (refer to 4 ...
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... Freescale Semiconductor, Inc. Bus Operation S0 S2 CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D0 HALT BR BG BGACK 4.5.4 Double Bus Fault A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following: 1 ...
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... Freescale Semiconductor, Inc. completed (during execution of the exception handler routine or later) does not cause a dou- ble bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a dou- ble bus fault. The QUICC continues to retry the same bus cycle as long as the external hardware requests it ...
Page 126
... Freescale Semiconductor, Inc. Bus Operation received BG through the arbitration process, and BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. Figure 4- flowchart showing the detail involved in bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles. ...
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... Freescale Semiconductor, Inc. CLKO1 A31–A0 D31– DSACK1–DSACK0 BR BG BGACK NOTE: BR has synchronous timing. BR has asynchronous timing. Figure 4-35. Bus Arbitration Timing Diagram—Idle Bus Case For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 128
... Freescale Semiconductor, Inc. Bus Operation CLKO1 A31–A0 D31– R/W DSACK1–DSACK0 BR (IN) BG (OUT) BGACK (IN) NOTE: BR has synchronous timing. BR has synchronous timing. Figure 4-36. Bus Arbitration Timing Diagram—Active Bus Case 4.6.1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR. This signal can be wire-ORed to indicate to the QUICC that some external device requires control of the bus ...
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... Freescale Semiconductor, Inc. 4.6.2 Bus Grant The QUICC supports operand coherency; thus operand transfer requires multiple bus cycles, the QUICC does not release the bus until the entire transfer is complete. The asser- tion therefore subject to the following constraints: • The minimum time for BG assertion after BR is asserted depends on internal synchro- nization. • ...
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... Freescale Semiconductor, Inc. Bus Operation Once an external device receives the bus and asserts BGACK, it should negate BR remains asserted after BGACK is asserted, the QUICC assumes that another device is requesting the bus and prepares to issue another BG. 4.6.4 Bus Arbitration Control The bus arbitration control unit in the QUICC is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the QUICC are internally synchronized in a maximum of two cycles of the clock ...
Page 131
... Freescale Semiconductor, Inc. RAB STATE R—BUS REQUEST A—BUS GRANT ACKNOWLEDGE B—BUS CYCLE IN PROGRESS Figure 4-37. Bus Arbitration State Diagram 4.6.5 Slave (Disable CPU32+) Mode Bus Arbitration When configured in the slave mode, the QUICC follows the bus arbitration mechanism de- scribed in 4.6 Bus Arbitration. When acting as one or more of the QUICC internal masters (refresh cycles, IDMA, and SDMA), the QUICC will output the BR signal ...
Page 132
... Freescale Semiconductor, Inc. Bus Operation master at the same time, the one having the highest priority becomes bus master first. The sequence of the protocol in normal slave mode is as follows: 1. The QUICC asserts BR. 2. The QUICC waits for the assertion of BG and the negation of BGACK to indicate that the bus is available ...
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... Freescale Semiconductor, Inc the 68040 requests the bus at the same time that a QUICC internal master is re- questing the bus, the BR040ID bits are used to determine who will acquire the bus first. 4. When the QUICC no longer needs the bus, it deasserts BB and asserts BG. ...
Page 134
... Freescale Semiconductor, Inc. Bus Operation The QUICC has another mechanism to assign priorities to the bus masters. A new pin called bus clear in (BCLRI) is defined. BCLRI indicates to the QUICC that a request is being made for the QUICC to release the system bus. The QUICC will then clear all internal bus masters with an arbitration ID smaller than the programmed value of the bus clear in ID (BCLRIID) in the MCR ...
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... Freescale Semiconductor, Inc. 4.6.6 Slave (Disable CPU32+) Mode Bus Exceptions The reset and bus error master mode support also applies to the slave mode. There is a difference, however, in supporting halt and retry as explained in the following paragraphs. 4.6.6.1 HALT. The QUICC transfer operation may be suspended at any time by asserting HALT to the QUICC ...
Page 136
... Freescale Semiconductor, Inc. Bus Operation C1 CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TM0 R TBI D31–D0 Figure 4-41. MC68EC040 Internal Registers Read Cycle C1 CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TT0 R TBI D31–D0 Figure 4-42. MC68EC040 Internal Registers Write Cycle ...
Page 137
... Freescale Semiconductor, Inc CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TM0 R TBI D31–D0 AVECO IACK7 IACK1 Figure 4-43. MC68EC040 Autovector Operation Timing CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TM0 R TBI D31–D8 D7–D0 IACK7 IACK1 Figure 4-44. MC68EC040 Interrupt Acknowledge Cycle MC68360 USER’ ...
Page 138
... Freescale Semiconductor, Inc. Bus Operation 4.6.8 Show Cycles The QUICC can perform data transfers with its internal modules without using the external bus, but when debugging desirable to have address and data information appear on the external bus. These external bus cycles, called show cycles, are distinguished by the fact that AS is not asserted externally ...
Page 139
... Freescale Semiconductor, Inc. CLKO1 A31–A0 FC3–FC0 SIZ1–SIZ0 R/W AS D31–D0 BKPT Figure 4-45. Show Cycle Timing Diagram 4.7 RESET OPERATION The QUICC has reset control logic to determine the cause of reset, synchronize it if neces- sary, and assert the appropriate reset lines. The reset control logic can independently drive five different internal lines: 1 ...
Page 140
... Freescale Semiconductor, Inc. Bus Operation Table 4-9. Reset Source Summary Type External Hard Reset (RESETH) External Soft Reset (RESETS) Power-Up Software Watchdog Sys Prot Double Bus Fault Sys Prot 1 Loss of Clock Reset Instruction CPU32+ NOTES: 1.The reset behavior is this case is dependent on the PLL programming (see 6.9.3.9 CLKO Control Register (CLKOCR)). ...
Page 141
... Freescale Semiconductor, Inc. Once RESETH and RESETS negate, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle of the reset exception processing begins. CLKO1 VCO LOCK ...
Page 142
... Freescale Semiconductor, Inc. Bus Operation RESETS does not restore the Boot CS0 since the intent of RE- SETS is to not reset the memory controller. Note that the CPU will still fetch the SP and PC from $0 and $4, therefore a system implementing RESETS must have a device or register mapped to 0 and 4 at all times ...
Page 143
... Freescale Semiconductor, Inc. SECTION 5 CPU32+ The CPU32+, the second instruction processing module of the M68300 family, is based on the industry-standard MC68000 core processor. Like the original CPU32, it has many fea- tures of the MC68010 and MC68020 as well as unique features suited for high-performance processor applications. The CPU32+ provides a significant performance increase over the MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000 family ...
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... Freescale Semiconductor, Inc. CPU32+ aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception. The CPU32+ has four bits (SZ1, SZ0 and SZC1, SCZ0) in the software status word (SSW) that are new or have changed definitions ...
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... Freescale Semiconductor, Inc. • Enhanced Breakpoint Instruction • Trace on Change of Flow • Table Lookup and Interpolate (TBL) Instruction • LPSTOP Instruction • Hardware BKPT Signal, Background Mode • Fully Static Implementation A block diagram of the CPU32+ is shown in Figure 5-1. The major blocks depicted operate in a highly independent fashion that maximizes concurrences of operation while managing the essential synchronization of instruction execution and bus operation ...
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... Freescale Semiconductor, Inc. CPU32+ Figure 5-2. Loop Mode Instruction Sequence 5.1.3 Vector Base Register The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions ...
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... Freescale Semiconductor, Inc. field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored. 5.1.5 Addressing Modes Addressing in the CPU32+ is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility elim- inates the need for extra instructions to store register contents in memory ...
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... Freescale Semiconductor, Inc. CPU32+ 5.2.1 Programming Model The CPU32+ programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can only use the registers of the user model. The supervisor programming model, which supplements the user programming model, is used by CPU32+ system programmers who wish to protect sensitive operating system functions ...
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... Freescale Semiconductor, Inc Figure 5-4. Supervisor Programming Model Supplement 5.2.2 Registers Registers D7–D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32- bit), and quad-word (64-bit) operations. Registers and the USP and SSP are address registers that may be used as software SPs or base address registers. Register A7 (shown as A7 and A7' in Figure 5-3 and Figure 5- register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level ...
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... Freescale Semiconductor, Inc. CPU32+ SYSTEM BYTE TRACE ENABLE SUPERVISOR/USER STATE 5.3 INSTRUCTION SET The following paragaphs describe the CPU32+ instruction set. A description of the instruc- tion format, the operands used by the instructions, and a summary of the instructions by cat- egory are included. Complete programming information is provided in the M68000PM/AD, M68000 Family Programmer’ ...
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... Freescale Semiconductor, Inc. Mnemonic Description ABCD Add Decimal with Extend ADD Add ADDA Add Address ADDI Add Immediate ADDQ Add Quick AND Logical AND ANDI Logical AND Immediate ASL Arithmetic Shift Left ASR Arithmetic Shift Right Bcc Branch Conditionally (16 Tests) BCHG ...
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... Freescale Semiconductor, Inc. CPU32+ 5.3.1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user-mode programs should execute unchanged on a more advanced processor and that supervisor-mode programs and excep- tion handlers should require only minimal alteration. The CPU32+ can be thought intermediate member of the M68000 family. Object code from an MC68000 or MC68010 may be executed on the CPU32+, and many of the instruction and addressing mode extensions of the MC68020 are also supported ...
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... Freescale Semiconductor, Inc. 15 OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) Figure 5-6. Instruction Word General Format Besides the operation code, which specifies the function to be performed, an instruction de- fines the location of every operand for the function ...
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... Freescale Semiconductor, Inc. CPU32+ Xn Index register [An] Address extension cc Condition code d # Displacement Example 16-bit displacement ea Effective address # data Immediate data; a literal integer label Assembly program label list List of registers Example: D3–D0 [...] Bits of an operand Examples: [7] is bit 7; [31:24] are bits 31–24 (...) ...
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... Freescale Semiconductor, Inc. Not equal to > Greater than Greater than or equal to < Less than Less than or equal to Logical AND V Logical OR Logical exclusive OR ~ Invert; operand is logically complemented BCD Binary-coded decimal, indicated by subscript Example: Source BCD source operand. LSW Least significant word MSW ...
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... Freescale Semiconductor, Inc. CPU32+ Table 5-2. Instruction Set Summary Opcode Source 10 + Destination ABCD ADD Source + Destination ADDA Source + Destination ADDI Immediate Data + Destination ADDQ Immediate Data + Destination ADDX Source + Destination + X AND Source Destination ANDI Immediate Data ANDI to CCR Source CCR If supervisor state ...
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... Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Continued) Opcode Compare Rn < lower-bound or CMP2 Rn > upper-bound and Set Condition Codes If condition false then (Dn – 1 DBcc If Dn –1 then DIVS Destination/Source DIVSL DIVU Destination/Source DIVUL EOR Source Destination EORI Immediate Data Destination ...
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... Freescale Semiconductor, Inc. CPU32+ Table 5-2. Instruction Set Summary (Continued) Opcode If supervisor state MOVE USP then USP else TRAP If supervisor state MOVEC then else TRAP Registers Destination MOVEM Source Registers MOVEP Source Destination MOVEQ Immediate Data If supervisor state then Rn Destination [DFC] or Source ...
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... Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Concluded) Opcode RTS (SP) PC Destination 10 – Source 10 – X SBCD If Condition True Scc then 1s Destination else 0s Destination If supervisor state STOP then Immediate Data else TRAP SUB Destination – Source SUBA Destination – Source SUBI Destination – ...
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... Freescale Semiconductor, Inc. CPU32+ Table 5-3. Condition Code Computations Operations X ABCD * ADD, ADDI, ADDQ * ADDX * AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI, — CLR, EXT, NOT, TAS, TST CHK — CHK2, CMP2 — SUB, SUBI, SUBQ * SUBX * CMP, CMPI, CMPM — ...
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... Freescale Semiconductor, Inc. Table 5-3. Condition Code Computations (Continued) Note: The following notations apply to this table only. — = Not affected U = Undefined ? = See special definition = General case ... Boolean AND V = Boolean OR 5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of transferring and storing address and data. MOVE instructions transfer byte, word, and long- word operands from memory to memory, memory to register, register to memory, and reg- ister to register ...
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... Freescale Semiconductor, Inc. CPU32+ operand sizes valid for data operations. Address operands consist bits. The clear and negate instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV instructions include: • Word multiply to produce a long-word product • Long-word multiply to produce a long-word or quad-word product • ...
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... Freescale Semiconductor, Inc. Table 5-5. Integer Arithmetic Operations Operand Instruction Syntax Dn, ea ADD ADDA ADDI # data ea ADDQ # data ea Dn, Dn ADDX – (An), – (An) CLR ea CMP CMPA CMPI # data ea CMPM (An) +, (An) + CMP2 DIVS/DIVU Dr: DIVSL/DIVUL ea , Dr:Dq Dn EXT Dn EXTB MULS/MULU Dh:Dl NEG ea NEGX SUB Dn, ea ...
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... Freescale Semiconductor, Inc. CPU32+ Operand Instruction Syntax AND Dn, ea ANDI # data ea EOR Dn, ea EORI # data ea NOT Dn, ea ORI # data ea TST ea 5.3.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions. ...
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... Freescale Semiconductor, Inc. Table 5-7. Shift and Rotate Operations Operand Instruction Syntax Dn, Dn ASL # data Dn ea Dn, Dn ASR # data Dn ea Dn, Dn LSL # data Dn ea Dn, Dn LSR # data Dn ea Dn, Dn ROL # data Dn ea Dn, Dn ROR # data Dn ea Dn, Dn ROXL # data Dn ea Dn, Dn ...
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... Freescale Semiconductor, Inc. CPU32+ Table 5-8. Bit Manipulation Operations Operand Instruction Syntax Dn, ea BCHG # data ea Dn, ea BCLR # data ea Dn, ea BSET # data ea Dn, ea BTST # data ea 5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD) ...
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... Freescale Semiconductor, Inc. Table 5-10. Program Control Operations Operand Instruction Syntax Bcc label DBcc Dn label Scc ea BRA label BSR label JMP ea JSR ea NOP none RTD # d RTR none RTS none To specify conditions for change in program control, condition codes must be substituted for the letters "cc" in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. — ...
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... Freescale Semiconductor, Inc. CPU32+ Table 5-11. System Control Operations Operand Instruction Syntax ANDI # data , SR EORI # data , MOVE SR, ea USP, An MOVEA An, USP Rc, Rn MOVEC Rn, Rc Rn, ea MOVES ORI # data , SR RESET none RTE none STOP # data LPSTOP # data BKPT # data BGND none CHK ...
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... Freescale Semiconductor, Inc. the result is 0, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true. Table 5-12 lists each condition test. Mnemonic Not available for the Bcc instruction. =Boolean AND +=Boolean OR N=Boolean NOT 5 ...
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... Freescale Semiconductor, Inc. CPU32+ 5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries. As shown in Figure 5-7, the function is linear within the range 32768 entries within this range are as given in Table 5-13 . Table 5-13. Standard Usage Entries Entry Number 128* ...
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... Freescale Semiconductor, Inc. 5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure 5-8), the data from Example 1 has been compressed by limiting the maximum value of the indepen- dent variable. Instead of the range 65535 limited 1023. The table has been compressed to only five entries, but up to 256 levels of interpolation are allowed between entries ...
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... Freescale Semiconductor, Inc. CPU32+ Thus, Dx now contains the following bit pattern: 31 NOT USED Table Entry Offset Dx [8:15 Interpolation Fraction Dx [0:7] = $8E = 142 Using this information, the table instruction calculates dependent variable 1331 (142 (1966 – 1311)) / 256 = 1674 The function chosen for Examples 1 and 2 is linear between data points. If another function had been used, interpolated values might not have been identical ...
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... Freescale Semiconductor, Inc. Table 5-15. T8-Bit Independent Variable Entries (Subroutine) The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subrou- tine. The following value has been calculated for independent variable X: ...
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... Freescale Semiconductor, Inc. CPU32+ The new range for 4096; however, since a left shift fills the least significant digits of the word with zeros, the interpolation fraction can only have one of 16 values. After the shift operation, Dx contains the following value: 31 NOT USED ...
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... Freescale Semiconductor, Inc. Rounding yields: The second result is preferred. The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results: L0: TBLSN TBLSN TBLSN ADD.L Dx, Dm Long addition avoids problems with carry ADD.L Dm, Dl ASR ...
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... Freescale Semiconductor, Inc. CPU32+ The UNLK instruction removes a stack frame from the end of the list by loading an address into the SP and pulling the value at that address from the stack. When the instruction oper- and is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from both the stack and the linked list ...
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... Freescale Semiconductor, Inc. available at the supervisor level, but execution of some instructions is not permitted at the user level. There are separate SPs for each level. The S-bit in the SR indicates privilege level and determines which SP is used for stack operations. The processor identifies each bus access (supervisor or user mode) via function codes to enforce supervisor and user access levels ...
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... Freescale Semiconductor, Inc. CPU32+ If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the SR and PC are restored to the values saved on the supervisor stack, and execution resumes at the restored PC address, with access level determined by the S-bit of the restored SR. If the frame was generated by a bus error or an address error exception, the entire processor state is restored from the stack ...
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... Freescale Semiconductor, Inc. Table 5-16. Exception Vector Assignments Vector Offset Vector Number Dec Hex 0 0 000 1 4 004 2 8 008 3 12 00C 4 16 010 5 20 014 6 24 018 7 28 01C 8 32 020 9 36 024 10 40 028 11 44 02C 12 48 030 13 52 ...
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... Freescale Semiconductor, Inc. CPU32+ 5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset for details of reset processing. As exception processing begins, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing ...
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... Freescale Semiconductor, Inc. 5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on its relative importance to system operation. Priority assignments are shown in Table 5-17. Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest priorities. Exception processing for exceptions that occur simultaneously is done by priority, from high- est to lowest ...
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... Freescale Semiconductor, Inc. CPU32+ 5.5.2 Processing of Specific Exceptions The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed. 5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RE- SET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception ...
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... Freescale Semiconductor, Inc FETCH VECTOR # 0 OTHERWISE (VECTOR # 0) FETCH VECTOR # 1 OTHERWISE (VECTOR # 1) PREFETCH 3 WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION Figure 5-11. Reset Operation Flowchart When the aborted bus cycle is an instruction prefetch, the processor will not initiate excep- tion processing unless the prefetched information is used. For example branch instruc- tion flushes an aborted prefetch, that word is not accessed, and no exception occurs ...
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... Freescale Semiconductor, Inc. CPU32+ tiated while an instruction is executing. Several bus error stack format organizations are uti- lized to provide additional information regarding the nature of the fault. First, any register altered by a faulted-instruction EA calculation is restored to its initial value. Then a special status word (SSW) is placed on the stack. The SSW contains specific infor- mation about the aborted access— ...
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... Freescale Semiconductor, Inc. The vector number for the TRAP instruction is internally generated—part of the number comes from the instruction itself. The trap vector number, PC value, and a copy of the SR are saved on the supervisor stack. The saved PC value is the address of the instruction that follows the instruction that generated the trap ...
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... Freescale Semiconductor, Inc. CPU32+ tor table entry number 14. The stacked PC is the address of the RTE instruction that discovered the format error. 5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it con- tains a word bit pattern that does not correspond to the bit pattern of the first word of a legal ...
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... Freescale Semiconductor, Inc. • MOVE to SR • MOVE USP • MOVEC • MOVES • OR Immediate to SR • RESET • RTE • STOP Exception processing for privilege violations is nearly identical to that for illegal instructions. The instruction is fetched and decoded. If the processor determines that a privilege violation has occurred, exception processing begins before instruction execution ...
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... Freescale Semiconductor, Inc. CPU32+ At the present time, T1– undefined condition reserved by Motorola for future use. Exception processing for trace starts at the end of normal processing for the traced instruc- tion and before the start of the next instruction. Exception processing follows the regular sequence ...
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... Freescale Semiconductor, Inc. Interrupt recognition and subsequent processing are based on internal interrupt request sig- nals (IRQ7–IRQ1) and the current priority set in SR priority mask I2–I0. Interrupt request level 0 (IRQ7–IRQ1 negated) indicates that no service is requested. When an interrupt of level 1 through 6 is requested via IRQ6–IRQ1, the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed ...
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... Freescale Semiconductor, Inc. CPU32+ the system context in existence prior to the exception. The RTE instruction is designed to accomplish this task. When RTE is executed, the processor examines the stack frame on top of the supervisor stack to determine valid and determines what type of context restoration must be per- formed ...
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... Freescale Semiconductor, Inc. TP—BERR Frame Type The TP field defines the class of the faulted bus operation. Two bus error exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking Operand or prefetch bus fault 1 = Exception processing bus fault MV— ...
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... Freescale Semiconductor, Inc. CPU32+ RR—Rerun Write Cycle after RTE RR will be set if the faulted bus cycle was a released write. A released write is one that is overlapped. If the write is completed (rerun) in the exception handler, the RR bit should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon re- turn from the exception handler ...
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... Freescale Semiconductor, Inc. 5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32+ defines four fault types: released write faults, faults during exception processing, faults dur- ing MOVEM operand transfer, and faults on any other bus cycle. ...
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... Freescale Semiconductor, Inc. CPU32+ taken prior to restarting the instruction. If the exception handler does not alter the stacked SR trace bits, the trace is requeued when the instruction is started. The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted upon return from the handler. This avoids problems with bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location ...
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... Freescale Semiconductor, Inc. The SSW for a fault within an exception contains the following bit pattern SZC1 TR B1 TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. The contents of the faulted exception stack frame are included in the bus fault stack frame. ...
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... Freescale Semiconductor, Inc. CPU32+ word and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields should be left unchanged. The bus controller uses the modified fault address and SIZ field to rerun the complete released write cycle. Manipulating the stacked SSW can cause unpredictable results because RTE checks only the RR bit to determine if a bus cycle must be rerun ...
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... Freescale Semiconductor, Inc. 5. De-allocate the stack and return control to the faulted program. 5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart. In some situations it may be necessary to rerun all the operand transfers for a faulted instruction rather than con- tinue from a faulted operand. Clearing the MV bit in the stacked SSW converts a type III fault into a type II fault ...
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... Freescale Semiconductor, Inc. CPU32+ exception frame on top of the stack, and resume execution at the exception handler address. 5.5.4 CPU32+ Stack Frames The CPU32+ generates three different stack frames: four-word frames, six-word frames, and twelve-word bus error frames. 5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exceptions ...
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... Freescale Semiconductor, Inc. frames of other M68000 family members. The only internal machine state required in the CPU32+ stack frame is the bus controller state at the time of the error and a single register. Bus operation in progress at the time of a fault is conveyed by the SSW SZC1 TR B1 The bus error stack frame is 12 words in length ...
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... Freescale Semiconductor, Inc. CPU32 +$02 +$ +$08 +$0C +$10 +$14 +$ Figure 5-15. Format $C—BERR Stack for Prefetches and Operands 15 SP +$02 +$ +$08 +$0C +$10 +$14 +$ Figure 5-16. Format $C—BERR Stack on MOVEM Operand 15 SP +$02 +$ +$08 +$0C +$10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) ...