MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 171

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

7.5 ACKNOWLEDGE BUS CYCLES
Bus transfers with transfer type signals TT1 and TT0 = $3 are classified as acknowledge
bus cycles. The following paragraphs describe interrupt acknowledge and breakpoint
acknowledge bus cycles that use this encoding.
7.5.1 Interrupt Acknowledge Bus Cycles
When a peripheral device requires the services of the M68040 or is ready to send
information that the processor requires, it can signal the processor to take an interrupt
exception. The interrupt exception transfers control to a routine that responds
appropriately. The peripheral device uses the active-low interrupt priority level signals
(IPL2–IPL0) to signal an interrupt condition to the processor and to specify the priority level
for the condition. Refer to Section 8 Exception Processing for a discussion on the IPL≈
levels and IPEND.
The status register (SR) of the M68040 contains an interrupt priority mask (I2–I0 bits). The
value in the interrupt mask is the highest priority level that the processor ignores. When an
interrupt request has a priority higher than the value in the mask, the processor makes the
request a pending interrupt. IPL2–IPL0 must maintain the interrupt request level until the
M68040 acknowledges the interrupt to guarantee that the interrupt is recognized. The
M68040 continuously samples IPL2–IPL0 on consecutive rising edges of BCLK to
synchronize and debounce these signals. An interrupt request that is held constant for two
consecutive clock periods is considered a valid input. Although the protocol requires that
the request remain until the processor runs an interrupt acknowledge cycle for that
interrupt value, an interrupt request that is held for as short a period as two clock cycles
can be recognized. Figure 7-19 is a flowchart of the procedure for making an interrupt
pending.
MOTOROLA
When the processor recognizes TA at the end of a clock, the bus cycle is terminated,
but TIP remains asserted if the processor is ready to begin another bus cycle.
Otherwise, the processor negates TIP during the first half of the next clock. The
processor also three-states the data bus during the first half of the next clock following
termination of the write cycle. When the last write transfer is terminated, LOCKE is
negated. The processor also negates LOCK if the next bus cycle is not a read-modify-
write.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
7- 29