MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 381

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
B.3.1 Access Control Registers
Each ACU has two independent access control registers (ACRs). The instruction ACU con-
tains the instruction access control registers (IACR0 and IACR1). The data ACU contains
the data access control registers (DACR0 and DACR1). Both ACRs provide and control sta-
tus information for access control of memory in the MC68EC040. Only programs that exe-
cute in the supervisor mode using the MOVEC instruction can directly access the ACRs.
The 32-bit ACRs each define blocks of MC68EC040:address space for access control.
These blocks of address space can overlap or be separate, and are a minimum of 16
Mbytes. Three blocks are used with two user-defined attributes, cachability control and
optional write protection. The ACRs specify a block of address space as serialized noncach-
able for peripheral selections and as write-through for shared blocks of address space in
multi-processing applications. The ACRs can be configured to support many embedded
control applications while maintaining cache integrity. Refer to Section 4 Instruction and
Data Caches for details concerning cachability. Figure B-4 illustrates the ACR format.
ADDRESS BASE
ADDRESS MASK
E—Enable
S—Supervisor/User Mode
MOTOROLA
31
LOGICAL ADDRESS BASE
This 8-bit field is compared with physical address bits A31–A24. Addresses that match in
this comparison (and are otherwise eligible) are accessible.
This 8-bit field contains a mask for the ADDRESS BASE field. Setting a bit in the AD-
DRESS MASK field causes the processor to ignore the corresponding bit in the AD-
DRESS BASE field. Setting some of the ADDRESS MASK bits to ones obtains blocks of
memory larger than 16 Mbytes. The low-order bits of this field are normally set to define
contiguous blocks larger than 16 Mbytes, although contiguous blocks are not required.
This bit enables and disables transparent translation of the block defined by this register.
Refer to Section 3 Memory Management Unit (Except MC68EC040 and
MC68EC040V) for details on transparent translation.
This field specifies the way FC2 is used in matching an address:
0 = Access control disabled.
1 = Access control enabled.
00 =Match only if FC2 = 0 (user mode access).
01 =Match only if FC2 = 1 (supervisor mode access).
10, 11 =Ignore FC2 when matching.
Figure B-4. MC68EC040 Access Control Register Format
24 23
Freescale Semiconductor, Inc.
LOGICAL ADDRESS MASK E
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
16 15 14 13 12 11 10
S
0
0
0 U1 U0
9
MC68EC040
8
7
0
6
CM
5
REV2.3 (01/31/2000)
4
0
3
0
W
2
1
0
B-5
0
0

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