MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 401

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
C.2.1 Bus Arbitration and Snooping
Bus arbitration and snooping are not allowed during low-power stop mode. If an alternate
bus master requires ownership, arbitration must occur before the processor is allowed to
enter low-power stop mode. This is achieved by externally decoding the LPSTOP
broadcast cycle and negating the BG signal before the termination of the cycle, allowing
bus arbitration to complete at the end of the cycle.
If the MC68040V or the MC68EC040V is the bus master during low-power stop mode,
lowest power consumption cannot be achieved due to the DC loads on the processor
output pins. To achieve maximum power savings, arbitrate bus mastership away from the
processor during the LPSTOP broadcast cycle.
In a single bus master system the caches do not need to be shut down prior to the
execution of LPSTOP. In a multi-master system, the programmer is responsible for
providing a shut down sequence for the caches.
C.2.2 Low Frequency Operation
In addition to the low-power mode of operation the MC68040V and MC68EC040V provide
a low frequency mode of operation. This mode of operation can be entered one of in two
ways: directly from reset by asserting LFO prior to negating RSTI; or by asserting LFO
prior to generating the interrupt or reset when exiting the low-power stop mode. In the
former case, the BCLK input can be changed as long as the frequency is 0–16 MHz and
the minimum pulse width constraints are met. Normal operation can be resumed through
the low-power stop mode and deasserting LFO.
C.2.3 Changing BCLK Frequency
The frequency of the BCLK input can be changed only during the low-power stop or low
frequency modes of operation. Once in the low-power stop mode and SCD is asserted,
BCLK can be disabled or its frequency can be changed. Reducing the frequency or
removing the BCLK input is not required for proper operation, but is an additional power
saving measure. BCLK can be removed during the low-power stop mode as an additional
system power saving measure. However, it is not necessary for normal operation and has
no effect on the MC68040V's or MC68EC040V's power consumption.
MOTOROLA
M68040 USER’S MANUAL
C-5
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