MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 76

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Each ATC entry consists of a physical address, attribute information from a corresponding
page descriptor, and a tag that contains a logical address and status information. Figure
3-21, which illustrates the entry and tag fields, is followed by field definitions listed in
alphabetical order.
CM—Cache Mode
FC2—Function Code Bit 2 (Supervisor/User)
G—Global
Logical Address
M—Modified
MOTOROLA
This field selects the cache mode and accesses serialization as follows:
Section 4 Instruction and Data Caches provides detailed information on caching
modes, and Section 7 Bus Operation provides information on serialization.
This bit contains the function code corresponding to the logical address in this entry.
FC2 is set for supervisor mode accesses and cleared for user mode accesses.
When set, this bit indicates the entry is global. Global entries are not invalidated by the
PFLUSH instruction variants that specify nonglobal entries, even when all other
selection criteria are satisfied.
This 13-bit field contains the most significant logical address bits for this entry. All 16
bits of this field are used in the comparison of this entry to an incoming logical address
when the page size is 4 Kbytes. For 8-Kbytes pages, the least significant bit of this field
is ignored.
The modified bit is set when a valid write access to the logical address corresponding to
the entry occurs. If the M-bit is clear and a write access to this logical address is
attempted, the M68040 suspends the access, initiates a table search to set the M-bit in
the page descriptor, and writes over the old ATC entry with the current page descriptor
information. The MMU then allows the original write access to be performed. This
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
ENTRY
TAG
* For 4-Kbyte page sizes this field uses address bits 31–12; for 8-Kbyte page sizes, bits 31–13.
U1
V
U0
G
FC2
S
Freescale Semiconductor, Inc.
Figure 3-21. ATC Entry and Tag Fields
For More Information On This Product,
CM
LOGICAL ADDRESS*
Go to: www.freescale.com
M68040 USER'S MANUAL
M
W
R
PHYSICAL ADDRESS*
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