A80386DX33 Intel, A80386DX33 Datasheet

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... Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata ...

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... Intel386 TM 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT CONTENTS 1 PIN ASSIGNMENT 1 1 Pin Description Table 2 BASE ARCHITECTURE 2 1 Introduction 2 2 Register Overview 2 3 Register Descriptions 2 4 Instruction Set 2 5 Addressing Modes 2 6 Data Types 2 7 Memory Organization Space 2 9 Interrupts 2 10 Reset and Initialization ...

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CONTENTS 5 FUNCTIONAL DATA (Continued Bus Transfer Mechanism Introduction Memory and I O Spaces Memory and I O Organization Dynamic Data Bus Sizing ...

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... PIN ASSIGNMENT The Intel386 DX pinout as viewed from the top side of the component is shown by Figure 1-1 Its pinout as viewed from the Pin side of the component is Figure 1-2 Figure 1-1 Intel386 TM DX PGA Pinout View from Top Side Table 1-1 Intel386 Signal Pin ...

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... Intel386 DX MICROPROCESSOR PIN DESCRIPTION TABLE The following table lists a brief description of each pin on the Intel386 DX The following definitions are used in these descriptions The named signal is active LOW I Input signal O Output signal I O Input and Output signal No electrical connection For a more complete description refer to Section 5 2 Signal Description ...

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... DX to suspend execution of the current program and execute an interrupt acknowledge function NMI I NON-MASKABLE INTERRUPT REQUEST is a non-maskable input that signals the Intel386 DX to suspend execution of the current program and execute an interrupt acknowledge function RESET I RESET suspends any operation in progress and places the Intel386 ...

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... These attri- butes include its location size type (i e stack code or data) and protection characteristics Each task on an Intel386 DX can have a maximum of 16 381 segments four gigabytes each thus provid- ing 64 terabytes (trillion bytes) of virtual memory to ...

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... The Flags Register is a 32-bit register named EFLAGS The defined bits and bit fields within EFLAGS shown in Figure 2-3 control certain opera- tions and indicate status of the Intel386 DX The lower 16 bits (bit 0 – 15) of EFLAGS contain the 16-bit flag register named FLAGS which is most ...

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... Intel386 DX MICROPROCESSOR TM NOTE 0 indicates Intel reserved do not define see section Figure 2-3 Flags Register VM (Virtual 8086 Mode bit 17) The VM bit provides Virtual 8086 Mode within Protected Mode If set while the Intel386 Protected Mode the Intel386 DX will switch to Virtual 8086 operation handling ...

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... TF (Trap Enable Flag bit 8) TF controls the generation of exception 1 trap when single-stepping through code When TF is set the Intel386 DX generates an exception 1 trap after the next instruction is executed When TF is reset exception 1 traps occur only as a function of the break- point addresses loaded into debug registers DR0– ...

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... DX LMSW instructions work in an identical fashion to the LMSW instruction on the 80286 ( only operates on the low-order 16-bits of CR0 and it ignores the new bits in CR0 ) New Intel386 DX oper- ating systems should use the MOV CR0 Reg in- struction The defined CR0 bits are described below ...

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... The PAGE FAULT LINEAR ADDRESS REGISTER PAGE DIRECTORY BASE REGISTER NOTE 0 indicates Intel reserved Do not define SEE SECTION Figure 2-6 Control Registers 2 and 3 Intel386 DX MICROPROCESSOR TM error code pushed onto the page fault handler’s stack when it is invoked provides additional status ...

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... Test Registers Two registers are used to control the testing of the RAM CAM (Content Addressable Memories) in the Translation Lookaside Buffer por- tion of the Intel386 DX TR6 is the command test register and TR7 is the data register which contains the data of the Translation Lookaside buffer test ...

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... Immediate to Memory The operands can be either bits long As a general rule when executing code written for the Intel386 DX (32-bit code) operands are bits when executing existing 80286 or 8086 code (16-bit code) operands are bits Prefixes can be added to all instructions which override the default ...

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... Intel386 DX MICROPROCESSOR Intel386 TM DX Instructions Table 2-2a Data Transfer GENERAL PURPOSE MOV Move operand PUSH Push operand onto stack POP Pop operand off stack PUSHA Push all registers on stack POPA Pop all registers off stack XCHG Exchange Operand Register XLAT Translate ...

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... Jump if not overflow JNP JPO Jump if not parity parity odd JNS Jump if not sign JO Jump if overflow JP JPE Jump if parity parity even JS Jump if Sign Intel386 DX MICROPROCESSOR TM Table 2-2f Program Control Instructions (Continued) UNCONDITIONAL TRANSFERS CALL Call procedure task RET Return from procedure ...

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... Intel386 DX MICROPROCESSOR ADDRESSING MODES Addressing Modes Overview The Intel386 DX provides a total of 11 addressing modes for instructions to specify operands The ad- dressing modes are optimized to allow the efficient execution of high level languages such as C and FORTRAN and they cover the vast majority of data ...

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... In Real Mode the default size for operands and addresses is 16-bits Regardless of the default precision of the operands or addresses the Intel386 DX is able to execute ei- ther 16 or 32-bit instructions This is specified via the use of override prefixes Two prefixes the Operand ...

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... Bit A single bit quantity Bit Field A group contiguous bits which spans a maximum of four bytes Bit String A set of contiguous bits on the Intel386 DX bit strings can gigabits long Byte A signed 8-bit quantity Unsigned Byte An unsigned 8-bit quantity Integer (Word) A signed 16-bit quantity Long Integer (Double Word) A signed 32-bit quan- tity All operations assume a 2’ ...

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... Figure 2-10 Intel386 TM DX Supported Data Types Intel386 DX MICROPROCESSOR TM 231630 –52 21 ...

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... Intel386 DX MICROPROCESSOR MEMORY ORGANIZATION Introduction Memory on the Intel386 DX is divided up into 8-bit quantities (bytes) 16-bit quantities (words) and 32-bit quantities (dwords) Words are stored in two consecutive bytes in memory with the low-order byte at the lowest address the high order byte at the high ...

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... I O SPACE The Intel386 DX has two distinct physical address spaces Memory and I O Generally peripherals are placed space although the Intel386 DX also supports memory-mapped peripherals space consists of 64K bytes it can be divided into 64K 8-bit ports 32K 16-bit ports or 16K 32-bit ports ...

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... Table 2-5 summarizes the possi- ble interrupts for the Intel386 DX and shows where the return address points The Intel386 DX has the ability to handle up to 256 different interrupts exceptions In order to service the interrupts a table with up to 256 interrupt vec- tors must be defined The interrupt vectors are sim- ...

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... NMI interrupt to inhibit further INTR interrupts Software Interrupts A third type of interrupt exception for the Intel386 DX is the software interrupt An INT n instruction causes the processor to execute the interrupt serv- ice routine pointed to by the nth vector in the inter- ...

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... Intel386 DX detects a problematic condition The Intel386 DX then immediately invokes the appropriate exception service routine The state of the Intel386 DX is such that the instruction causing the exception can be re- started If the exception service routine has taken care of the problematic condition the instruction will ...

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... PE Bit 0) 3 The Code Segment Register (CS) will have its Base Ad- dress set to FFFF0000H and Limit set to 0FFFFH 4 All undefined bits are Intel Reserved and should not be used 5 DX register always holds component and stepping iden- tifier (see 5 7) EAX register holds self-test signature if self- ...

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... Intel386 DX MICROPROCESSOR TESTABILITY Self-Test The Intel386 DX has the capability to perform a self- test The self-test checks the function of all of the Control ROM and most of the non-random logic of the part Approximately one-half of the Intel386 DX can be tested during self-test Self-Test is initiated on the Intel386 DX when the ...

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... LINEAR ADDRESS PHYSICAL ADDRESS NOTE 0 indicates Intel reserved Do not define SEE SECTION Breakpoint Instruction A single-byte-opcode breakpoint instruction is avail- able for use by software debuggers The breakpoint opcode is 0CCh and generates an exception 3 trap when executed In typical use a debugger program can ‘‘plant’’ the breakpoint instruction at all desired ...

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... Int e l reserved Do not define 0 LEN R W LEN R W LEN R W LEN NOTE 0 indicates Intel reserved Do not define SEE SECTION tion breakpoints must have a length of 1 (LENi 00) Encoding of the LENi field is as follows Usage of Least LENi Breakpoint Significant Bits in Encoding Field Width Breakpoint Address Register ...

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... If either set then the associated breakpoint (as defined by the linear address in DRi the length in LENi and the usage criteria in RWi) is enabled If either set and the Intel386 DX detects the ith breakpoint condition then the exception 1 han- dler is invoked When the Intel386 DX performs a task switch to a ...

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... This bit is set if the exception 1 handler was invoked due to a task switch occurring to a task having an Intel386 DX TSS with the T bit set (See Figure 4-15a) Note the task switch into the new task oc- curs normally but before the first instruction of the ...

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... Protected Mode Operation The LOCK prefix on the Intel386 DX even in Real Mode is more restrictive than on the 80286 This is due to the addition of paging on the Intel386 DX in Protected Mode and Virtual 8086 Mode Paging makes it impossible to guarantee that repeated string instructions can be LOCKed The Intel386 DX can’ ...

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... Mode allows the Intel386 DX to run all of the existing 8086 and 80286 software while providing a sophisti- cated memory management and a hardware-assist- ed protection mechanism Protected Mode allows the use of additional instructions especially opti- ...

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... Paging provides an additional memory management mechanism which operates only in Protected Mode Paging provides a means of managing the very large segments of the Intel386 DX As such paging oper- ates beneath segmentation The paging mechanism translates the protected linear address which comes from the segmentation unit into a physical address ...

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... DESCRIPTOR TABLES INTRODUCTION The descriptor tables define all of the segments which are used in an Intel386 DX system There are three types of tables on the Intel386 DX which hold descriptors the Global Descriptor Table Local De- scriptor Table and the Interrupt Descriptor Table All of the tables are variable length memory arrays ...

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... The IDT should be at least 256 bytes in size in order to hold the descriptors for the 32 Intel Reserved Interrupts Every interrupt used by a sys- tem must have an entry in the IDT The IDT entries ...

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... The De- scriptor Privilege Level DPL is a two-bit field which specifies the protection level 0– 3 associated with a segment The Intel386 DX has two main categories of seg- ments system segments and non-system segments 31 SEGMENT BASE 15 0 BASE 31 ...

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... D 0 then 16-bit operands and 16-bit addressing e modes are assumed Therefore all existing 80286 code segments will execute on the Intel386 DX as- suming the D bit is set 0 Another attribute of code segments is determined by the conforming C bit Conforming segments C can be executed and shared by programs at differ- ...

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... Descriptor contents are valid DPL least privileged level at which a task may access the gate WORD COUNT 0 –31 the number of parameters to copy from caller’s stack to the called procedure’s stack The parameters are 32-bit quantities for Intel386 DESTINATION 16-bit Selector to the target code segment ...

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... B bit The word count field specifies the number of 16-bit quantities to copy for 80286 call gates and 32-bit quantities for Intel386 DX call gates The B bit controls the size of PUSHes when using a call gate if B ...

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... Intel386 DX MICROPROCESSOR TM Figure 4-10 Example Descriptor Selection 42 231630 –59 ...

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... SEGMENT DESCRIPTOR REGISTER SETTINGS The contents of the segment descriptor cache vary depending on the mode the Intel386 DX is operating in When operating in Real Address Mode the seg- ment base limit and other attributes within the seg- ment cache registers are defined as shown in Figure ...

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... Intel386 DX MICROPROCESSOR TM When operating in Protected Mode the segment base limit and other attributes within the segment cache registers are defined as shown in Figure 4-12 In Protected Mode each of these fields are defined Key Y fixed yes e N fixed per segment descriptor e p per segment descriptor descriptor must indicate ‘‘present’’ to avoid exception 11 ...

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... U expand up e Figure 4-13 Segment Descriptor Caches for Virtual 8086 Mode within Protected Mode (Segment Limit and Attributes are Fixed) Intel386 DX MICROPROCESSOR TM 0000FFFFH and the attributes are fixed indicate the segment is present and fully usable The virtual program executes at lowest privilege level ...

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... Privilege Levels TASK PRIVILEGE At any point in time a task on the Intel386 DX al- ways executes at one of the four privilege levels The Current Privilege Level (CPL) specifies the task’s privilege level A task’s CPL may only be changed by control transfers through gate descrip- ...

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... CPL RPL and DPL as described above Any time an instruction loads data segment registers ( GS) the Intel386 DX makes protection validation checks Selectors loaded in the registers must refer only to data segments or readable code segments The data access rules are ...

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... Intel386 DX MICROPROCESSOR TM Table 4-3 Descriptor Types Used for Control Transfer Control Transfer Types Intersegment within the same privilege level Intersegment to the same or higher privilege level Interrupt within task may change CPL Intersegment to a lower privilege level (changes task CPL) Task Switch ...

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... NOTE BIT MAP OFFSET must be DFFFH s Type 9 Available Intel386 TM DX TSS e Type B Busy Intel386 TM DX TSS e Figure 4-15a Intel386 Intel386 DX MICROPROCESSOR TM DX TSS and TSS Registers TM 231630 –64 49 ...

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... TSS selector The Intel386 DX supports both 80286 and Intel386 DX style TSSs Figure 4-16 shows a 80286 TSS The limit of an Intel386 DX TSS must be great- er than 0064H (002BH for a 80286 TSS) and can be as large as 4 Gigabytes In the additional TSS ...

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... ESC or WAIT instruction if the Task Switched and Monitor coprocessor extension bits are both set ( The T bit in the Intel386 DX TSS indicates that the processor should generate a debug exception when switching to a task If T new task a debug exception 1 will be generated ...

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... Intel provides a tool which allows the system designer an easy method of constructing the data structures needed for a Protected Mode Intel386 DX system This tool is the builder BLD-386 BLD-386 lets the operating system writer specify all of the segment descriptors discussed in the previous ...

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... Paging Organization PAGE MECHANISM The Intel386 DX uses two levels of tables to trans- late the linear address (from the segmentation unit) into a physical address There are three compo- nents to the paging mechanism of the Intel386 DX ...

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... For example the remaining 31 bits could be used to indicate where on the disk the page is stored The A (Accessed) bit 5 is set by the Intel386 DX for both types of entries before a read or write access occurs to an address covered by the entry The D ...

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... Access bit If P Table Entry indicating that the page is in memory the Intel386 DX will update the Access and Dirty bits as needed and fetch the operand The upper 20 bits of the linear address read from the page table will ...

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... Mode addressing on a per task basis Through the use of paging the one megabyte address space of the Virtual Mode task can be mapped to anywhere in the 4 gigabyte linear address space of the Intel386 DX Like Real Mode Virtual Mode effective address segment offsets) that exceed 64K byte will ...

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... Figure 4-24 Virtual 8086 Environment Memory Management erating system code between multiple 8086 applica- tions Figure 4-24 shows how the Intel386 DX paging hardware enables multiple 8086 programs to run un- der a virtual memory demand paged system Protection and I O Permission Bitmap All Virtual 8086 Mode programs execute at privilege ...

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... I O Permission Bitmap contained in the Intel386 DX Task State Segment The I O Permission Bitmap automatically used by the Intel386 DX in Virtual 8086 Mode is illustrated by Figures 4 15a and 4-15b The I O Permission Bitmap can be viewed – 64 Kbit bit string which begins in memory at offset ...

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... FLAGS image containing the VM bit position while the processor is executing in Protected Mode That is one way to enter Virtual 8086 mode is to switch to a task with an Intel386 DX TSS that has the VM bit in the EFLAGS image The other way is to execute a 32-bit IRET instruction at privilege ...

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... The IRET instruction will perform the inverse of the above sequence Only the extended Intel386 DXs IRET instruction (operand size and must be executed at level 0 to change the VM bit to 1 ...

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... The Intel386 DX can relinquish control of its local buses to allow mastership by other devices such as direct memory access channels When relinquished HLDA is the only output pin driven by the Intel386 DX providing near-complete isolation of the proces- sor from its system The near-complete isolation characteristic is ideal when driving the system from ...

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... READY is asserted During any write operation (and during halt cycles and shutdown cycles) the Intel386 DX always drives all 32 signals of the data bus even if the current bus size is 16-bits Address Bus (BE0 BE3 A2 through A31) ...

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... Intel386 DX-to- coprocessor communication use I O addresses 800000F8H through 800000FFH so A31 HIGH in conjunction with M IO LOW allows simple genera- tion of the coprocessor select signal The Byte Enable outputs BE0 – BE3 dicate which bytes of the 32-bit data bus are in- ...

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... This three-state output indicates that a valid bus cy- cle definition and address ( BE0 –BE3 and A2 – A31) is being driven at the Intel386 DX pins It is asserted during T1 and T2P bus states (see Non-pipelined Address and Pipelined Address for additional information on bus states TRANSFER ACKNOWLEDGE (READY ) This input indicates the current bus cycle is com- plete and the active bytes indicated by BE0 – ...

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... HOLD asserted and is in the bus Hold Acknowl- edge state The Hold Acknowledge state offers near-complete signal isolation In the Hold Acknowledge state HLDA is the only signal being driven by the Intel386 DX The other output signals or bidirectional signals (D0–D31 BE0 – BE3 A2– A31 W R ...

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... RESET (RESET) This input signal suspends any operation in progress and places the Intel386 known reset state The Intel386 DX is reset by asserting RESET for 15 or more CLK2 periods (80 or more CLK2 periods before requesting self test) When RESET is assert- ed all other input pins are ignored and all other bus ...

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... Signal Summary Table 5-4 summarizes the characteristics of all Intel386 DX signals Table 5-4 Intel386 Signal Name Signal Function CLK2 Clock D0–D31 Data Bus BE0 –BE3 Byte Enables A2 –A31 Address Bus W R Write-Read Indication D C Data-Control Indication M IO Memory-I O Indication LOCK Bus Lock Indication ...

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... Since a bus cycle requires a minimum of two bus states (equal to two processor clock periods) data can be transferred between external devices and the Intel386 maximum rate of one 4-byte Dword every two processor clock periods for a max- imum bus bandwidth of 66 megabytes second (In- ...

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... Figure 5-4 Physical Memory and I O Spaces Memory and I O Organization The Intel386 DX datapath to memory and I O spaces can be 32 bits wide or 16 bits wide When 32-bits wide memory and I O spaces are organized naturally as arrays of physical 32-bit Dwords Each ...

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... Asserting BS16 during ‘‘upper half only’’ reads causes the Intel386 DX to read data on the lower 16 bits of the data bus and ignore data on the upper 16 bits of the data bus Data that would have been read from D16– D31 (as indicated by BE2 and BE3 ) will instead be read from D0 – ...

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... BUS FUNCTIONAL DESCRIPTION combina Introduction The Intel386 DX has separate parallel buses for data and address The data bus is 32-bits in width and bidirectional The address bus provides a 32-bit value using 30 signals for the 30 upper-order ad- dress bits and 4 Byte Enable signals to directly indi- ...

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... Intel386 DX MICROPROCESSOR TM K-map for A1 signal (same as Figure 5-3) K-map for 16-bit BHE K-map for 16-bit BLE signal (same as A0 signal in Figure 5-3) Figure 5-7 Logic to Generate A1 BHE Table 5-8 Transfer Bus Cycles for Bytes Words and Dwords Physical Byte Address in Memory (low-order bits) ...

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... The data bus has a dynamic sizing feature support- ing 32- and 16-bit bus size Data bus size is indicated to the Intel386 DX using its Bus Size 16 (BS16 ) input All bus functions can be performed with either data bus size When the Intel386 DX bus is not performing one of ...

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... Intel386 DX MICROPROCESSOR TM The fastest Intel386 DX bus cycle requires only two bus states For example three consecutive bus read cycles each consisting of two bus states are shown by Figure 5-8 The bus states in each cycle are named T1 and T2 Any memory address may be accessed by such a two-state bus cycle if the ...

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... TM to begin in one memory bank while the current bus cycle is still activating another memory bank Figure 5-10 shows the general structure of the Intel386 DX with 2-bank and 4-bank interleaved memory Note each memory bank of the interleaved memory has full data bus width (32-bit data width typically unless ...

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... Negation of BS16 indicates a 32-bit size and assertion indicates a 16-bit bus size If 16-bit bus size is indicated the Intel386 DX auto- matically responds as required to complete the transfer on a 16-bit data bus Depending on the size and alignment of the operand another 16-bit bus ...

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... During read or write cycles the data bus behaves as follows If the cycle is a read the Intel386 DX floats its data signals to allow driving by the external de- vice being addressed The Intel386 DX requires that all data bus pins valid logic state ...

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... Intel386 DX MICROPROCESSOR TM Bus States T1 first clock of a non-pipelined bus cycle (Intel386 DX drives new address and asserts ADS ) T2 subsequent clocks of a bus cycle when NA Ti idle state Th hold acknowledge state (Intel386 DX asserts HLDA) The fastest bus cycle consists of two states T1 and T2 Four basic bus states describe bus operation when not using pipelined address These states do include BS16 ...

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... Key Dn physical data pin logical data bit n e Figure 5-14 Asserting BS16 Intel386 DX MICROPROCESSOR TM 32 bits If BS16 was most recently asserted the size is defined as 16 bits When BS16 is asserted and two 16-bit bus cycles ...

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... Intel386 DX MICROPROCESSOR TM Key Dn physical data pin logical data bit n e Figure 5-15 Asserting BS16 generated for the two 16-bit bus cycles are closely related to each other The addresses are the same except BE0 and BE1 are always negated for the second cycle This is because data on D0 – D15 was ...

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... READY ADS is asserted by the Intel386 DX when the next address is issued The address pipelining option is controlled on a cycle-by-cycle basis with the NA input signal ...

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... T2I is entered instead of T2P (see Figure 5-19 Cycle 3) Provided the current bus cy- cle isn’t yet acknowledged by READY T2P will be entered as soon as the Intel386 DX does drive the next address External hardware should therefore observe the ADS confirmation the next address is actually being ...

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... During Figure 5-17 Cycle 1 therefore sampling be- gins in T2 Once NA the current cycle the Intel386 DX is free to drive a new address and bus cycle definition on the bus as early as the next bus state In Figure 5-16 Cycle 1 for ...

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... Intel386 DX MICROPROCESSOR TM Figure 5-19 Details of Address Pipelining During Cycles with Wait States 84 231630 –23 ...

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... Bus States T1 first clock of a non-pipelined bus cycle (Intel386 DX drives new ad- dress and asserts ADS ) T2 subsequent clocks of a bus cycle when NA asserted in the current bus cycle T2I subsequent clocks of a bus cycle when NA serted in the current bus cycle but there is not yet an internal bus request ...

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... A2–A31 such as may be required when BS16 is asserted by the external hardware To avoid conflict the Intel386 DX is designed with following two provisions 1) To avoid conflict BS16 must be negated in the ...

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... Those are read or write operands using only the low- er half of the data bus and write operands using only the upper half of the bus since the Intel386 DX simultaneously duplicates the write data on the low- er half of the data bus For these patterns of Byte ...

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... Four idle bus states Ti are inserted by the Intel386 DX be- tween the two interrupt acknowledge cycles allow- ing for compatibility with spec TRHRL of the 8259A Interrupt Controller During both interrupt acknowledge cycles D0– ...

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... Shutdown Indication Cycle The Intel386 DX shuts down as a result of a protec- tion fault while attempting to process a double fault Signaling its entrance into the shutdown state a shutdown indication cycle is performed The shut- down indication cycle is identified by the state of the bus definition signals shown Bus Cycle Def- ...

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... RESET should remain asserted for at least 15 CLK2 periods to ensure it is recognized throughout the In- tel386 DX and at least 80 CLK2 periods if Intel386 DX self-test is going to be requested at the falling edge RESET asserted pulses less than 15 CLK2 periods may not be recognized RESET pulses less ...

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... Provided the RESET falling edge meets setup and hold times t and t the internal processor clock 25 26 phase is defined at that time as illustrated by Figure 5-28 and Figure 7-7 A Intel386 DX self-test may be requested at the time RESET is negated by having the BUSY LOW level as shown in Figure 5-28 The self-test 20 requires (2 ) approximately 60 CLK2 periods to a ...

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... DX register The upper 8 bits of DX hold 03h as identification of the Intel386 DX compo- nent The lower 8 bits of DX hold an 8-bit unsigned binary number related to the component revision level The revision identifier begins chronologically with a value zero and is subject to change (typically ...

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... CLK2 periods before and after the CLK2 period in which RESET falling edge occurs 2 If self-test is requested the Intel386 DX outputs remain in their reset state as shown here and in Table 5-3 Figure 5-28 Bus Activity from Reset Until First Code Fetch ...

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... ERROR inputs of the Intel386 DX may also be used for the custom coprocessor inter- face if such hardware assist is desired These sig- nals can be tested by the Intel386 DX WAIT opcode (9Bh) The WAIT instruction will wait until the BUSY input is negated (interruptable by an NMI or ...

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... To calculate elapsed time for an instruction multiply the instruction clock count as listed in Table 6-1 below by the processor clock period ( for a 20 MHz Intel386 for a 25 MHz Intel386 DX and 30 ns for a 33 MHz Intel386 DX) For more detailed information on the encodings of instructions refer to section 6 2 Instruction Encod- ...

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... Intel386 DX MICROPROCESSOR TM Table 6-1 Intel386 INSTRUCTION FORMAT GENERAL DATA TRANSFER MOV Move e Register to Register Memory Register Memory to Register Immediate to Register Memory Immediate to Register (short form Memory to Accumulator (short form Accumulator to Memory (short form Register Memory to Segment Register Segment Register to Register Memory ...

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... Table 6-1 Intel386 DX Instruction Set Clock Count Summary (Continued) TM INSTRUCTION FORMAT SEGMENT CONTROL LDS Load Pointer LES Load Pointer LFS Load Pointer LGS Load Pointer LSS Load Pointer FLAG CONTROL CLC Clear Carry Flag e CLD Clear Direction Flag CLI Clear Interrupt Enable Flag ...

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... Intel386 DX MICROPROCESSOR TM Table 6-1 Intel386 DX Instruction Set Clock Count Summary (Continued) TM INSTRUCTION FORMAT ARITHMETIC (Continued) Register from Memory mod reg Memory from Register mod reg Immediate from Register Memory mod Immediate from Accumulator (short form SBB Subtract with Borrow e Register from Register ...

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... DX Instruction Set Clock Count Summary (Continued) Table 6-1 Intel386 TM INSTRUCTION FORMAT ARITHMETIC (Continued) DIV Divide (Unsigned) e Accumulator by Register Memory mod Divisor Byte Word Doubleword IDIV Integer Divide (Signed) e Accumulator By Register Memory mod Divisor Byte Word Doubleword AAD ASCII Adjust for Divide ...

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... Intel386 DX MICROPROCESSOR TM Table 6-1 Intel386 TM DX Instruction Set Clock Count Summary (Continued) INSTRUCTION FORMAT LOGIC (Continued) Register to Memory mod reg Memory to Register mod reg Immediate to Register Memory mod Immediate to Accumulator (Short Form TEST And Function to Flags No Result e Register Memory and Register ...

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... Table 6-1 Intel386 TM DX Instruction Set Clock Count Summary (Continued) INSTRUCTION FORMAT REPEATED STRING MANIPULATION (Continued) REPNE CMPS Compare String e (Find Match REP INS Input String REP LODS Load String REP MOVS Move String REP OUTS Output String REPE SCAS Scan String ...

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... From 80286 Task to Intel386 DX TSS From 80286 Task to Virtual 8086 Task (Intel386 DX TSS) From Intel386 DX Task to 80286 TSS From Intel386 DX Task to Intel386 DX TSS From Intel386 DX Task to Virtual 8086 Task (Intel386 DX TSS) Indirect Intersegment mod Protected Mode Only (Indirect Intersegment) Via Call Gate to Same Privilege Level ...

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... DX Instruction Set Clock Count Summary (Continued) Table 6-1 Intel386 TM INSTRUCTION FORMAT CONTROL TRANSFER (Continued) RET Return from CALL e Within Segment Within Segment Adding Immediate Intersegment Intersegment Adding Immediate Protected Mode Only (RET) to Different Privilege Level Intersegment Intersegment Adding Immediate to SP CONDITIONAL JUMPS NOTE Times Are Jump ‘ ...

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... Intel386 DX MICROPROCESSOR TM DX Instruction Set Clock Count Summary (Continued) Table 6-1 Intel386 TM INSTRUCTION FORMAT CONDITIONAL JUMPS (Continued) JNS Jump on Not Sign e 8-Bit Displacement Full Displacement JPE Jump on Parity Parity Even e 8-Bit Displacement Full Displacement JNP JPO Jump on Not Parity Parity Odd ...

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... DX Instruction Set Clock Count Summary (Continued) Table 6-1 Intel386 TM INSTRUCTION FORMAT CONDITIONAL BYTE SET (Continued) SETNB Set Byte on Not Below Above or Equal e To Register Memory SETE SETZ Set Byte on Equal Zero e To Register Memory SETNE SETNZ Set Byte on Not Equal Not Zero ...

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... From Intel386 DX Task to Intel386 DX TSS via Task Gate From Intel386 DX Task to virt 8086 md via Task Gate From virt 8086 md to 80286 TSS via Task Gate From virt 8086 md to Intel386 DX TSS via Task Gate From virt 8086 md to priv level 0 via Trap Gate or Interrupt Gate INT TYPE 3 ...

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... From Intel386 DX Task to Intel386 DX TSS via Task Gate From 80368 Task to virt 8086 Mode via Task Gate From virt 8086 Mode to 80286 TSS via Task Gate From virt 8086 Mode to Intel386 DX TSS via Task Gate From virt 8086 md to priv level 0 via Trap Gate or Interrupt Gate INTERRUPT RETURN ...

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... Intel386 DX MICROPROCESSOR TM Table 6-1 Intel386 DX Instruction Set Clock Count Summary (Continued) TM INSTRUCTION FORMAT PROCESSOR EXTENSION INSTRUCTIONS Processor Extension Escape TTT and LLL bits are opcode information for coprocessor PREFIX BYTES Address Size Prefix LOCK Bus Lock Prefix Operand Size Prefix Segment Override Prefix ...

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... Mode Notes d through g apply to Intel386 DX Real Address Mode and Intel386 DX Protected Virtual Address Mode d The Intel386 DX uses an early-out multiply algorithm The actual number of clocks depends on the position of the most significant bit in the operand (multiplier) Clock counts given are minimum to maximum To calculate actual clocks use the following formula ...

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... Figure does not show all fields Several smaller fields also appear in certain instruc- tions sometimes within the opcode bytes them- selves Table 6 complete list of all fields ap- pearing in the Intel386 DX instruction set Further ahead following Table 6-2 are detailed tables for each field l ...

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... Extensions of the Instruction Set With the Intel386 DX the 8086 80186 80286 in- struction set is extended in two orthogonal direc- tions 32-bit forms of all 16-bit instructions are added to support the 32-bit data types and 32-bit address- ing modes are made available for all instructions ref- ...

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... REGISTER (sreg) FIELD The sreg field in certain instructions is a 2-bit field allowing one of the four 80286 segment registers to be specified The sreg field in other instructions is a 3-bit field allowing the Intel386 DX FS and GS seg- ment registers to be specified 2-Bit sreg2 Field Segment ...

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... DS d16 00 111 000 001 010 011 100 101 110 111 Intel386 DX MICROPROCESSOR TM mod r m Effective Address 10 000 001 010 011 100 DS SI d16 a 10 101 DS DI d16 a 10 110 SS BP d16 a 10 111 DS BX d16 a 11 000 register see below 11 001 ...

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... Intel386 DX MICROPROCESSOR TM Encoding of 32-bit Address Mode with ‘‘mod r m’’ byte (no ‘‘s-i-b’’ byte present) mod r m Effective Address 00 000 DS EAX 00 001 DS ECX 00 010 DS EDX 00 011 DS EBX 00 100 s-i-b is present 00 101 DS d32 00 110 DS ESI 00 111 DS EDI 01 000 ...

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... SS ESP (scaled index 101 SS EBP (scaled index 110 DS ESI (scaled index 111 DS EDI (scaled index) a NOTE Mod field in ‘‘mod r m’’ byte ss index base fields in ‘‘s-i-b’’ byte Intel386 DX MICROPROCESSOR index 000 001 d8 a 010 d8 a 011 d8 ...

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... Intel386 DX MICROPROCESSOR ENCODING OF OPERATION DIRECTION (d) FIELD In many two-operand instructions the d field is pres- ent to indicate which operand is considered the source and which is the destination d Direction of Operation 0 Register Memory - - Register k ‘‘reg’’ Field Indicates Source Operand ‘‘mod r m’’ or ‘‘mod ss index base’’ Indicates ...

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... DESIGNING FOR ICE -Intel386 TM DX EMULATOR USE The Intel386 DX in-circuit emulator products are ICE-Intel386 DX 25 MHz or 33 MHz (both referred to as ICE-Intel386 DX emulator) The ICE-Intel386 DX emulator probe module has several electrical and mechanical characteristics that should be taken into consideration when designing the hardware ...

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... Intel386 DX MICROPROCESSOR TM Figure 7-2 Processor Module Target-Adapter Cable and Isolation Board Dimensions 118 231630 –85 ...

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... Intel386 DX MICROPROCESSOR PACKAGE DIMENSIONS AND MOUNTING The initial Intel386 DX package is a 132-pin ceramic pin grid array (PGA) Pins of this package are ar- ranged 0 100 inch (2 54mm) center-to-center matrix three rows around A wide variety of available sockets allow low inser- tion force or zero insertion force mountings and a ...

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... Intel386 DX MICROPROCESSOR TM Table 8 1 Several Socket Options for 132-Pin PGA Low insertion force (LIF) soldertail 55274-1 Amp tests indicate 50% reduction in insertion force compared to machined sockets Other socket options Zero insertion force (ZIF) soldertail 55583-1 Zero insertion force (ZIF) Burn-in version 55573-2 ...

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... Zero insertion force soldertail (for test and burn-in use) 2XX-6568-00-3302 Textool Products Electronic Products Division 3M (1410 West Pioneer Drive Irving Texas 75601 Phone 214-259-2676) Intel386 DX MICROPROCESSOR TM 231630 –86 courtesy Textool Products 3M 231630 –48 121 ...

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... Intel386 DX MICROPROCESSOR PACKAGE THERMAL SPECIFICATION The Intel386 DX is specified for operation when case temperature is within the range – The case temperature may be measured in any envi- ronment to determine whether the Intel386 DX is within specified operating range Figure 8 2 Measuring Intel386 Table 8 2 Intel386 ...

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... ELECTRICAL DATA 9 1 INTRODUCTION The following sections describe recommended elec- trical connections for the Intel386 DX and its electri- cal specifications 9 2 POWER AND GROUNDING Power Connections The Intel386 DX is implemented in CHMOS III and CHMOS IV technology and has modest power re- quirements However its high clock frequency and ...

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... BUSY and ERROR I Output Leakage Current LO I Supply Current CC CLK2 40 MHz with 20 MHz Intel386 e CLK2 50 MHz with 25 MHz Intel386 e CLK2 66 MHz with 33 MHz Intel386 e C Input Capacitance IN C Output Capacitance OUT C CLK2 Capacitance CLK NOTES 1 The min value not 100% tested b ...

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... A C spec measurement is defined by Figure 9-1 In- puts must be driven to the voltage levels indicated by Figure 9-1 when A C specifications are mea- sured Intel386 DX output delays are specified with minimum and maximum limits measured as shown The minimum Intel386 DX delay times are hold times NOTES 1 Input waveforms have from ...

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... Intel386 DX MICROPROCESSOR Specification Tables Functional Operating Range Table 9-4 33 MHz Intel386 Symbol Parameter Operating Frequency t1 CLK2 Period t2a CLK2 High Time t2b CLK2 High Time t3a CLK2 Low Time t3b CLK2 Low Time t4 CLK2 Fall Time t5 CLK2 Rise Time t6 A2– A31 Valid Delay t7 A2– ...

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... A C Specification Tables Functional Operating Range Table 9-4 33 MHz Intel386 Symbol Parameter t21 D0– D31 Read Setup Time t22 D0– D31 Read Hold Time t23 HOLD Setup Time t24 HOLD Hold Time t25 RESET Setup Time t26 RESET Hold Time t27 NMI INTR Setup Time ...

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... Intel386 DX MICROPROCESSOR Specification Tables Functional Operating Range Table 9-5 25 MHz Intel386 Symbol Parameter Operating Frequency t1 CLK2 Period t2a CLK2 High Time t2b CLK2 High Time t3a CLK2 Low Time t3b CLK2 Low Time t4 CLK2 Fall Time t5 CLK2 Rise Time t6 A2– A31 Valid Delay t7 A2– ...

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... A C Specification Tables Functional Operating Range Table 9-5 25 MHz Intel386 Symbol Parameter t21 D0 – D31 Read Setup Time t22 D0 – D31 Read Hold Time t23 HOLD Setup Time t24 HOLD Hold Time t25 RESET Setup Time t26 RESET Hold Time t27 NMI INTR Setup Time ...

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... Intel386 DX MICROPROCESSOR Specification Tables Functional Operating Range Table MHz Intel386 Symbol Parameter Operating Frequency t CLK2 Period 1 t CLK2 High Time 2a t CLK2 High Time 2b t CLK2 Low Time 3a t CLK2 Low Time 3b t CLK2 Fall Time 4 t CLK2 Rise Time – A31 Valid Delay ...

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... A C Specification Tables Functional Operating Range Table 9-6 20 MHz Intel386 Symbol Parameter t RESET Hold Time 26 t NMI INTR Setup Time 27 t NMI INTR Hold Time 28 t PEREQ ERROR 29 Setup Time t PEREQ ERROR 30 Hold Time NOTES 1 Float condition occurs when maximum output current becomes less than I ...

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... Intel386 DX MICROPROCESSOR Test Loads C 120 pF on A2– A31 D0– D31 BE0 – BE3 LOCK HLDA C includes all parasitic capacitances L Figure 9 Test Load Figure 9-4 Input Setup and Hold Timing 132 Timing Waveforms 231630– ADS Figure 9-3 CLK2 Timing 231630 –39 ...

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... Figure 9-5 Output Valid Delay Timing 231630– 79 Figure 9-5a Write Data Valid Delay Timing (25 MHz 33 MHz) Figure 9-5c Write Data Valid Delay Timing (20 MHz) Intel386 DX MICROPROCESSOR TM 231630 –41 231630 –80 Figure 9-5b Write Data Hold Timing (25 MHz 33 MHz) 231630 –81 ...

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... Intel386 DX MICROPROCESSOR Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (C NOTE This graph will not be linear outside of the Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (C NOTE This graph will not be linear outside of the C 134 120 pF) ...

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... Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (C NOTE This graph will not be linear outside of the Typical Output Rise Time Versus Load Capacitance at Maximum Operating Temperature NOTE This graph will not be linear outside of the C Intel386 231630 –83 range shown L 231630 – ...

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... Intel386 DX MICROPROCESSOR TM Figure 9-6 Output Float Delay and HLDA Valid Delay Timing The second internal processor phase following RESET high-to-low transition (provided t Figure 9-7 RESET Setup and Hold Timing and Internal Phase 136 231630 –42 231630 –43 and t are met ...

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... REVISION HISTORY This Intel386 DX data sheet version -005 contains updates and improvements to previous versions A revi- sion summary is listed here for your convenience The sections significantly revised since version -001 are Sequence of exception checking table added Instruction restart revised TLB testing revised ...

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... Double page faults do not raise double fault exception ERROR Figure 5-21 BS16 timing altered Figure 5-26 READY Figure 5-28 ERROR Corrected Encoding of Register Field Chart Chapter 7 Updated ICE-Intel386 DX information Remove preliminary stamp on 25 MHz A C Specifications Remove preliminary stamp on 33 MHz A C Specifications 138 Typ value corrected ...

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... Bits 3 4 and 5 of the ‘‘mod r m’’ byte corrected for the LTR instruction Table 8-2 Reference to Figure 6-4 should be reference Figure 8-2 Table 8-2 Note 4 added The sections significantly revised since version -008 are Table 9 MHz I Intel386 DX MICROPROCESSOR TM specifications updated CC 139 ...