MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 128
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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MC68360RC25K
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Bus Operation
4.6.1 Bus Request
External devices capable of becoming bus masters request the bus by asserting BR. This
signal can be wire-ORed to indicate to the QUICC that some external device requires control
of the bus. The QUICC is effectively at a lower bus priority level than the external device and
relinquishes the bus after it has completed the current bus cycle (if one has started). If no
BGACK is received while the BR is active, the QUICC remains bus master once BR is
negated. This prevents unnecessary interference with ordinary processing if the arbitration
circuitry inadvertently responds to noise or if an external device determines that it no longer
requires use of the bus before it has been granted mastership.
4-52
DSACK1–DSACK0
BGACK (IN)
NOTE:
Figure 4-36. Bus Arbitration Timing Diagram—Active Bus Case
BG (OUT)
D31–D0
A31–A0
BR (IN)
CLKO1
BR has synchronous timing.
BR has synchronous timing.
R/W
DS
AS
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
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