GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 15
GCIXP1240AC
Manufacturer Part Number
GCIXP1240AC
Description
IC MPU NETWORK 232MHZ 432-BGA
Manufacturer
Intel
Specifications of GCIXP1240AC
Rohs Status
RoHS non-compliant
Processor Type
Network
Features
32-bit StrongARM RISC Core
Speed
232MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
432-BGA
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Other names
837152
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
GCIXP1240AC
Manufacturer:
MOT
Quantity:
5 510
Status:
Specification Update
Example B – CTX_SWAP optional token.
Original code
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], ctx_swap
Workaround 1
SRAM[WRITE, $x2, sAddr,1, 2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1],ctx_swap
Workaround 2
SRAM[WRITE, $x1, sAddr, 0, 3], sig_done
SRAM[UNLOCK, --, sAddr, 0, 1]
CTX_ARB[SRAM]
Example C - When the priority queue is used, both requests must use the
same queue.
Original code
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], priority, ctx_swap
Workaround 1
SRAM[WRITE, $x2, sAddr, 1, 2], priority
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], priority, ctx_swap
Workaround 2
SRAM[WRITE, $x1, sAddr, 0, 3], priority, sig_done
SRAM[UNLOCK, --, sAddr, 0, 1], priority
CTX_ARB[SRAM]
Example D – correctly handling the defer optional token.
Original code
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], ctx_swap, defer[1]
alu[$x3, --, b, r3]
Workaround 1
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
alu[$x3, --, b, r3]
SRAM[WRITE, $x2, sAddr, 1, 2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], ctx_swap
Workaround 2
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
alu[$x3, --, b, r3]
SRAM[WRITE, $x1, sAddr, 0, 3], sig_done
SRAM[UNLOCK, --, sAddr, 0, 1]
Ctx_arb[SRAM]
NoFix
Intel
®
IXP1240 Network Processor
Errata
15