EE80C188XL20 Intel, EE80C188XL20 Datasheet - Page 12

• Manufacturer Part Number: EE80C188XL20
• Description: IC MPU 16BIT 5V 20MHZ 68PLCC
• Manufacturer: Intel

Specifications of EE80C188XL20

• Processor Type: 80C186
• Features: XL suffix, 16-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: Intel186
• Device Core: 80188
• Device Core Size: 16b
• Frequency (max): 20MHz
• Instruction Set Architecture: CISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863554

80C186XL 80C188XL
NOTE
Pin names in parentheses apply to the 80C188XL
12
BHE
(RFSH)
ALE QS0
WR QS1
RD QSMD
ARDY
Name
Pin
Type
Pin
O
O
O
O
I
Input
Type
A(L)
S(L)
Output
States
H(Z)
R(Z)
H(0)
R(0)
H(Z)
R(Z)
H(Z)
R(1)
Table 3 Pin Descriptions (Continued)
The BHE (Bus High Enable) signal is analogous to A0 in that it is
used to enable data on to the most significant half of the data bus
pins D15 – D8 BHE will be LOW during T
transferred and will remain LOW through T
need to be latched On the 80C188XL RFSH is asserted LOW to
indicate a refresh bus cycle
In Enhanced Mode BHE (RFSH) will also be used to signify DRAM
refresh cycles A refresh cycle is indicated by both BHE (RFSH) and
A0 being HIGH
Value
Address Latch Enable Queue Status 0 is provided by the processor
to latch the address ALE is active HIGH with addresses guaranteed
valid on the trailing edge
Write Strobe Queue Status 1 indicates that the data on the bus is to
be written into a memory or an I O device It is active LOW When
the processor is in Queue Status Mode the ALE QS0 and WR QS1
pins provide information about processor instruction queue
interaction
Read Strobe is an active LOW signal which indicates that the
processor is performing a memory or I O read cycle It is guaranteed
not to go LOW before the A D bus is floated An internal pull-up
ensures that RD QSMD is HIGH during RESET Following RESET
the pin is sampled to determine whether the processor is to provide
ALE RD and WR or queue status information To enable Queue
Status Mode RD must be connected to GND
Asynchronous Ready informs the processor that the addressed
memory space or I O device will complete a data transfer The
ARDY pin accepts a rising edge that is asynchronous to CLKOUT
and is active HIGH The falling edge of ARDY must be synchronized
to the processor clock Connecting ARDY HIGH will always assert
the ready condition to the CPU If this line is unused it should be tied
LOW to yield control to the SRDY pin
BHE
QS1
0
0
1
1
0
0
1
1
Value
QS0
A0
0
1
0
1
0
1
1
0
80C186XL BHE and A0 Encodings
Word Transfer
Byte Transfer on upper half of data bus
(D15 – D8)
Byte Transfer on lower half of data bus (D
Refresh
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue
Pin Description
Queue Operation
Function
1
when the upper byte is
3
and T
W
BHE does not
7
– D
0
)