PRIXP425BD Intel, PRIXP425BD Datasheet - Page 38

• Manufacturer Part Number: PRIXP425BD
• Description: IC NETWRK PROCESSR 533MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BD

• Processor Type: Network
• Features: XScale Core
• Speed: 533MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 866108

Intel
Functional Signal Descriptions
Table 10.
Table 11.
38
®
IXP42X Product Line and IXC1100 Control Plane Processor
UTOPIA-2 Interface (Sheet 2 of 2)
Expansion Bus Interface
UTP_IP_DATA[7:0]
UTP_IP_ADDR[4:0]
UTP_IP_FCO
†
EX_CLK
EX_ALE
EX_ADDR[23:0]
EX_WR_N
EX_RD_N
EX_CS_N[7:0]
EX_DATA[15:0]
EX_IOWAIT_N
EX_RDY[3:0]
†
For a legend of the Type codes, see
For a legend of the Type codes, see
Name
Name
Power
Reset
Reset
Power
On
H
H
H
Z
Z
Z
Z
Z
Z
On
Z
Z
Z
†
†
Reset
Reset
H
H
H
Z
0
1
1
1
0
VI
VI
Table 4 on page
Table 4 on page
Z
†
†
Type
Type
I/O
I/O
O
O
O
O
O
O
I
I
I
I
†
†
30.
30.
Input clock signal used to sample all expansion interface inputs and
clock all expansion interface outputs.
Address-latch enable used for multiplexed address/data bus accesses.
Used in Intel and Motorola* multiplexed modes of operation.
Expansion-bus address used as an output for data accesses over the
expansion bus. Also, used as an input during reset to capture device
configuration. These signals have a weak pull-up resistor attached
internally. Based on the desired configuration, various address signals
must be tied low in order for the device to operate in the desired mode.
Intel-mode write strobe / Motorola-mode data strobe
(EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N).
Intel-mode read strobe / Motorola-mode read-not-write
(EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N).
External chip selects for expansion bus.
Expansion-bus, bidirectional data
Data ready/acknowledge from expansion-bus devices. Expansion-bus
access is halted when an external device sets EX_IOWAIT_N to logic 0
and resume from the halted location once the external device sets
EX_IOWAIT_N to logic 1. This signal affects accesses that use
EX_CS_N[7:0] when the chip select is configured in Intel- or
Motorola-mode of operation.
Should be pulled high through a 10-KΩ resistor when not being utilized
in the system.
HPI interface ready signals. Can be configured to be active high or
active low. These signals are used to halt accesses using Chip Selects
7 through 4 when the chip selects are configured to operate in HPI
mode. There is one RDY signal per chip select. This signal only affects
accesses that use EX_CS_N[7:4].
Should be pulled low though a 10-KΩ resistor when not being utilized in
the system.
UTOPIA input data. Also known as RX_DATA.
Used by to the processor to receive data from an ATM
UTOPIA-Level-2-compliant PHY.
Should be pulled low through a 10-KΩ resistor when not being utilized
in the system.
Receive PHY address bus.
Used by the processor when operating in MPHY mode to poll and
select a single PHY at any one given time.
UTOPIA Input Data Flow Control Output signal: Also known as the
RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the PHY that
the processor is ready to accept data.
In MPHY configurations, UTP_IP_FCO is used to select which PHY will
drive the UTP_RX_DATA and UTP_RX_SOC signals. The PHY is
selected by placing the PHY’s address on the UTP_IP_ADDR and
bringing UTP_OP_FCO to logic 1 during the current clock, followed by
the UTP_OP_FCO going to a logic 0 on the next clock cycle.
•
•
Chip selects 0 through 7 can be configured to support Intel or
Motorola bus cycles.
Chip selects 4 through 7 can be configured to support TI HPI bus
cycles.
Description
Description
Datasheet