PRIXP425BD Intel, PRIXP425BD Datasheet - Page 88

• Manufacturer Part Number: PRIXP425BD
• Description: IC NETWRK PROCESSR 533MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BD

• Processor Type: Network
• Features: XScale Core
• Speed: 533MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 866108

Intel
Electrical Specifications
Table 44.
5.5.2.2
88
®
IXP42X Product Line and IXC1100 Control Plane Processor
PCI Bus Signal Timings
NOTES:
USB Interface
For timing parameters, see the USB 1.1 specification. The IXP42X product line and IXC1100
control plane processors’ USB 1.1 interface is a device or function controller only. The IXP42X
product line and IXC1100 control plane processors’ USB v 1.1 interface cannot be line-powered.
1. See the timing measurement conditions.
2. Parts compliant to the 3.3 V signaling environment.
3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than
4. RST# is asserted and de-asserted asynchronously with respect to CLK.
5. All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
7. Timing was tested with a 70-pF capacitor to ground.
8. For additional information, see the PCI Local Bus Specification , Rev. 2.2.
T
T
T
T
T
T
Symbol
clk2outb
clk2out
setupb
setup
rst-off
hold
do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has a setup of 12 ns for
33 MHz and 5 ns for 66 MHz.
the same time.
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
Clock to output for all point-to-point
signals. This is the PCI_GNT_N
and PCI_REQ_N(0) only.
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
Input setup time for all
point-to-point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
Input hold time from clock.
Reset active-to-output float delay
Parameter
10, 12
Min.
2
2
7
0
33 MHz
Max.
11
12
40
Min.
1
1
3
5
0
66 MHz
Max.
40
6
6
Units
ns
ns
ns
ns
ns
ns
Datasheet
1, 2, 5,
7,
1, 2, 5,
7,
4, 6, 7,
8
4, 7,
4, 7,
5, 6, 7,
8
Notes
8
8
8
8