LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 35

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LUPXA255A0C200

Manufacturer Part Number
LUPXA255A0C200
Description
IC MICRO PROCESSOR 200MHZ 256BGA
Manufacturer
Intel
Datasheets

Specifications of LUPXA255A0C200

Processor Type
XScale®
Speed
200MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
866868

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4.8
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Table 19. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
Table 20. Variable Latency I/O Interface AC Specifications
Memory Bus and PCMCIA AC Specifications
This section provides the timing information for these types of memory:
tromDSWH MD(31:0), DQM(3:0) write data setup to nWE de-asserted
tvlioASRW
tvlioDSWH
tvlioNPWE
tvlioRDYH
tvlioDHW
tromAHW
tromNWE
tvlioDSW
tromASW
tvlioCEH
tvlioDHR
tromCES
tromCEH
tvlioCES
Symbol
Symbol
tromDH
tromAS
tromAH
tromDS
tvlioAS
tvlioAH
SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes
ROM / Flash / Synchronous Fast Flash AC Specifications” on page
Variable latency I/O
page
Card interface (PCMCIA or Compact Flash)
Flash) AC Specifications” on page
Synchronous memories
page
35)
36)
MA(25:0) setubp to nCS asserted
MA(25:0) setup to nOE or nPWE asserted
MA(25:0) hold after nOE or nPWE de-asserted
nCS setup to nOE or nPWE asserted
nCS hold after nOE or nPWE de-asserted
MD(31:0), DQM(3:0) write data setup to nPWE asserted
MD(31:0), DQM(3:0) write data setup to nPWE de-
asserted
MD(31:0), DQM(3:0) hold after nPWE de-asserted
MD(31:0) read data hold after nOE de-asserted
RDY hold after nOE, nPWE de-asserted
nPWE, nOE high time between beats of write or read data
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) de-
asserted
MA(25:0) setup to nWE asserted
MA(25:0) hold after nWE de-asserted
nCS setup to nWE asserted
nCS hold after nWE de-asserted
MD(31:0), DQM(3:0) write data setup to nWE asserted
MD(31:0), DQM(3:0) write data hold after nWE de-asserted
nWE high time between beats of write data
(Table 20, “Variable Latency I/O Interface AC Specifications” on
(Table 22, “Synchronous Memory Interface AC Specifications 1” on
Description
Description
36)
(Table 21, “Card Interface (PCMCIA or Compact
MEMCLKs
Electrical Specifications
1
1
1
2
1
1
2
1
0
0
2
MEMCLKs
35)
(Table 19, “SRAM /
1
1
3
1
2
1
1
2
1
2
35

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