LUPXA255A0C300 Intel, LUPXA255A0C300 Datasheet
LUPXA255A0C300
Specifications of LUPXA255A0C300
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LUPXA255A0C300 Summary of contents
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... Intel® XScale™ Microarchitecture — Instruction Cache — Data Cache — “mini” Data Cache — Extensive Data Buffering Intel® Media Processing Technology ■ — Enhanced 16-bit Multiply — 40-bit Accumulator Flexible Clocking ■ — CPU clock from 100 to 400 MHz — ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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PXA255 Processor — Electrical, Mechanical, and Thermal Specification Contents 1.0 About This Document ............................................................................................ 7 2.0 Functional Overview ..............................................................................................7 3.0 Package Information ..............................................................................................8 3.1 Package Introduction..................................................................................... 8 3.1.1 3.2 Package Power Ratings ..............................................................................22 4.0 Electrical Specifications ...................................................................................... 22 4.1 Absolute ...
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PXA255 Processor — Electrical, Mechanical, and Thermal Specification Figures 1 Processor Block Diagram...................................................................................... 8 2 PXA255 processor .............................................................................................. 19 3 Power-On Reset Timing ...................................................................................... 31 4 Hardware Reset Timing ...................................................................................... 32 5 GPIO Reset Timing ............................................................................................. 33 6 Sleep Mode ...
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PXA255 Processor — Electrical, Mechanical, and Thermal Specification Revision History Date Revision March 2003 February 2004 Data Sheet -001 First public release of the EMTS -002 Updated 400 MHz Idle mode power. Description 5 ...
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PXA255 Processor — Electrical, Mechanical, and Thermal Specification 6 Data Sheet ...
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... A rich set of serial devices as well as general-system resources provide enough compute and connectivity capability for many applications. For details on the programming model and theory of operation of each of these units, refer to the Intel® PXA255 Processor Developer's Manual. For the processor block diagram, refer to Intel® ...
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... Table 3, “Pin and Signal Descriptions for the PXA255 Processor” on page 9 definitions for the PXA255 processor. physical characteristics of the PXA255 processor. 17x17mm mBGA Pinout — Ballpad No. Order” on page 20 processor. 8 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification RTC Color or Grayscale LCD Controller Int ...
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... SDRAM. Synchronous Static Memory clock enable. (output) SDCKE[0] OC Connect to the CKE pins of SMROM. The memory controller provides control register bits for de-assertion. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Function Signal Descriptions Package Information Reset State Sleep State ...
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... ICOCZ Memory controller alternate bus master request. GPIO[66] (input) Allows an external device to request the system bus from the memory controller. 10 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Reset State Sleep State Driven low Driven low Driven Low ...
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... L_DD[8]/ ICOCZ Memory controller alternate bus master request. GPIO[66] (input) Allows an external device to request the system bus from the Memory Controller. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Package Information Reset State Sleep State Pulled High - Note [3] ...
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... GPIO[35] FFDCD/ ICOCZ Full function UART data-carrier-detect. (input) GPIO[36] FFDSR/ ICOCZ Full function UART data-set-ready. (input) GPIO[37] 12 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Reset State Sleep State Pulled High - Note [3] Note[1] Pulled High - Note [3] Note[1] Pulled High - ...
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... L_DD[9]/ from the LCD controller to the external LCD panel. ICOCZ GPIO[67] MMC chip select 0. (output) Chip select 0 for the MMC controller. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Package Information Reset State Sleep State Pulled High - Note [3] ...
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... GPIO[84] USB Client Pins USB_P IAOAZ USB client positive. (bidirectional) USB_N IAOAZ USB client negative pin. (bidirectional) 14 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Reset State Sleep State Pulled High - Note [3] Note[1] Pulled High - Note [3] Note[1] ...
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... PXTAL OA required. 3.6864 MHz crystal output. No external caps are PEXTAL IA required. TXTAL OA 32 KHz crystal input. No external caps are required. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions 2 S clock is generated externally 2 S clock is generated by the 2 S controller controller ...
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... When nRESET is driven high, the processor starts execution from address 0. nRESET must remain low until the power supply is stable and the internal 3.6864 MHz oscillator has stabilized. 16 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Reset State Sleep State Note [2] ...
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... PCB. Ground supply for memory bus and PCMCIA pins. VSSN SUP Must be connected to the common ground plane on the PCB. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Signal Descriptions Package Information Reset State Sleep State Driven low during any reset sequence ...
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... Oscillator” on page 3-4 in the Intel® PXA255 Processor Developers Manual and Section 3.3.2, [2] “3.6864 MHz Oscillator” on page 3-4 of the Intel® PXA255 Processor Developers Manual for details on sleep- mode operation. GPIO sleep operation: The state of these pins is determined by the corresponding PGSRn during the transition into sleep mode. See Section 3.5.9, “ ...
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... Figure 2. PXA255 processor Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Package Information 19 ...
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... B11 FFDSR/GPIO[37] B12 USB_N B13 BTRXD/GPIO[42] B14 BTRTS/GPIO[45] B15 IRRXD/GPIO[46] B16 MMDAT C1 RDY/GPIO[18] C2 VSSN C3 L_DD[14]/GPIO[72] C4 VSSQ 20 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Ball # Signal Ball # C10 VCCQ F3 C11 VSSQ F4 C12 USB_P F5 C13 VCCQ F6 C14 VSSQ F7 C15 IRTXD/GPIO[47] ...
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... PLL_VCC J16 PLL_VSS K1 MA[8] K2 MA[9] K3 MD[19] K4 VCCN K5 MA[10] K6 MA[11] K7 VSSQ K8 VCC K9 VSSQ K10 VCC K11 nRESET_OUT Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Ball # Signal Ball # E14 VCCQ H7 E15 NSSPTXD/GPIO[83] H8 E16 NSSPSFRM/GPIO[82 nSDCS[0] H10 F2 nSDCS[3] H11 L9 VCC P6 L10 GPIO[0] P7 ...
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... Absolute Maximum Ratings This section provides the absolute maximum ratings for the processors. Do not exceed these parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not . guaranteed 22 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Ball # Signal Ball # N9 VCCN ...
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... The typical power consumption for the PXA255 processor is calculated using these conditions: • SSP, STUART, USB, PWM, Timer, I2S peripherals operating Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description VSS-0.3 VSS-0.3 VSS-0.3 VSS-0 ...
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... MHz idle mode, Maximum: V Typical: V =1.0V ccq I ccc I ccp P TOTAL 33 MHz idle mode, Maximum: V Typical: V =1.0V ccq 24 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Typical =1.65V =3.6V, Temp=100° ccq ccn /V =3.3V, Temp=Room ccn V Current 245 cc V and V ...
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... External Synchronous Memory fSDRAM_M Frequency, Mid Range High Voltage Range VVCC_H VCC, PLL_VCC Voltage, High Range fTURBO_H Turbo Mode Frequency, High Range External Synchronous Memory fSDRAM_H Frequency, High Range Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Typical V Current and V Current 9 ...
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... IOL_H strength output and I/O pins (VO=VOH) Output Low Current, all standard, low- IOL_L strength output and I/O pins (VO=VOH) 26 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Min 1.235 99.5 50 Table 10, “Standard Input, Output, and I/O Pin DC Operating ...
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... AC timings get with different loads. Input, Output, and I/O Pin AC Operating Conditions” high- and low-strength input, output, and I/O pins. All AC specification values are valid for the entire temperature range of the device. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Min 0.9*VCCN ...
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... Stabilization Time Board Specifications RP_XT Parasitic Resistance, TXTAL/TEXTAL to any node CP_XT Parasitic Capacitance, TXTAL/TEXTAL, total COP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL 28 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Table 13, “32.768-kHz Oscillator Specifications” Description Min Typical Max Units 10 ...
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... Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system; therefore not recommended. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Table 14 shows the 3.6864-MHz specifications. ...
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... On the processor important that the VCCQ power supply be powered up before or at the same time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up anytime within the specification shown in 30 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification 31. Figure 3 and Table Figure 3, “ ...
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... Delay between VCC, PLL_VCC stable tD_NRESET and nRESET de-asserted Delay between nRESET de-asserted tD_OUT and nRESET_OUT de--asserted Delay between nRESET_OUT tD_NCS0 deasserted and nCS0 asserted Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification and nRESET timing requirements indicated in t R_VCCQ t R_VCCN t D_VCCN t ...
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... GPIO reset is asserted (see Specifications” on page of GPIO reset. 32 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification 30. t DHW_OUT_A Note: nBA TT_FAULT and nVDD_F AULT must be high before nRESET is deasserted ...
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... GPIO reset. The lock detector has a maximum time of 350µs plus synchronization. 4.7.5 Sleep Mode Timing Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Mode Timing Specifications” on page 34 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification t A_GP[1] t DHW_OUT_A Description ...
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... VCC regulator must be stable within the stated maximum for the processor to function correctly. Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of the internal regulator and must be taken into account when designing the system. 34 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification t t D_PWR_R ...
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... RDY hold after nOE, nPWE de-asserted tvlioNPWE nPWE, nOE high time between beats of write or read data Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification (Table 20, “Variable Latency I/O Interface AC Specifications” on (Table 21, “Card Interface (PCMCIA or Compact 36) (Table 22, “Synchronous Memory Interface AC Specifications 1” on ...
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... MHz MEMCLK. It can be 99.5 MHz at the fastest. 3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest. 36 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description 1 Description MEMCLKs ...
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... SSP Module AC Timing Figure 8, “SSP AC Timing Definitions” on page 38 pin timing specifications are referenced to SCLK_C. Values for the parameters are given in Table 24, “SSP AC Timing Specifications” on page Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification T pclkdv T pclklv T pclkbv T pclkfv ...
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... Input hold from TCK nTRST TBSOV1 TDO valid delay TOF1 TDO float delay TOV12 All outputs (non-test) valid delay 38 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification T sfmv T sfmv T rxds Description shows the boundary scan test signal timing. Parameter Min Max 0 ...
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... Input hold from TCK all inputs TIH8 (non-test) 4.10 AC Test Conditions The AC specifications load indicated in Figure 9. AC Test Load Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Parameter Min Max 1.1 5.4 4.0 6.0 Section 4.5, “Targeted AC Specifications” on page 27 Figure 9 ...
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