LUPXA255A0C300 Intel, LUPXA255A0C300 Datasheet - Page 32

• Manufacturer Part Number: LUPXA255A0C300
• Description: IC MICRO PROCESSOR 300MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C300

• Processor Type: XScale®
• Speed: 300MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866869

Electrical Specifications
4.7.2
4.7.3
4.7.4
32
Figure 4. Hardware Reset Timing
Table 16. Hardware Reset Timing Specifications
Hardware Reset Timing
The timing sequences shown in hardware reset timing for hardware reset assumes stable power
supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings
indicated in
Watchdog Reset Timing
Watchdog reset is an internally generated reset and therefore has no external pin dependencies. The
nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for t
Refer to
GPIO Reset Timing
GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies
based on the frequency of clock selected, and if the clocks and power manager is in the frequency
change sequence when GPIO reset is asserted (see
Specifications” on page
of GPIO reset.
tDHW_NRESET
tDHW_OUT_A
tDHW_NCS0
tDHW_OUT
Symbol
nRESET_OUT
Figure 4, “Hardware Reset Timing” on page
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Section 4.7.1, “Power-On Timing” on page
nRESET
Minimum assertion time of nRESET
Delay between nRESET asserted and
nRESET_OUT asserted
Delay between nRESET de-asserted and
nRESET_OUT de-asserted
Delay between nReset_Out de-asserted
and nCS0 asserted
28.)
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
Note: nBA TT_FAULT and nVDD_F AULT must be high before nRESET is deasserted
Figure 5, “GPIO Reset Timing” on page 33
de-asserted or the PXA255 processor enters sleep mode.
or the Cotulla will enter Sleep Mode
Description
t
DHW_OUT_A
Section 4.6.1, “32.768-kHz Oscillator
32.
30.
0.001
18.1
Min
400
0
t
DHW_NRESET
Typical
shows the possible timing
—
0.001
t
Max
18.2
420
DHW_OUT
DHW_OUT
Units
ms
ms
ms
ns
.