CY7C344B-15JC Cypress Semiconductor Corp, CY7C344B-15JC Datasheet - Page 3

• Manufacturer Part Number: CY7C344B-15JC
• Description: IC EPLD 32MACROCELL 15NS 28-PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C344B-15JC

• Programmable Type: EPLD
• Number Of Macrocells: 32
• Voltage - Input: 5V
• Speed: 15ns
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1265

Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tions of this data sheet is not implied. Exposure to absolute
maximum ratings conditions for extended periods of time may
affect device reliability. The CY7C344B contains circuitry to
protect device pins from high-static voltages or electric fields;
however, normal precautions should be taken to avoid apply-
ing any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND
inputs must always be tied to an appropriate logic level (either
V
ed together directly at the device. Power supply decoupling
capacitors of at least 0.2 F must be connected between V
and GND. For the most effective decoupling, each V
should be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay t
When calculating synchronous frequencies, use t
puts are on the input pins. When expander logic is used in the
data path, add the appropriate maximum expander delay, t
to t
t
is the maximum data-path frequency for the synchronous con-
figuration.
When calculating external asynchronous frequencies, use
t
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
of 1/(t
frequency. The lowest of these frequencies is the maximum
data-path frequency for the asynchronous configuration.
The parameter t
device when driving other synchronous logic with positive in-
put hold times, which is controlled by the same synchronous
clock. If t
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common synchro-
nous clock under worst-case environmental and supply volt-
age conditions.
Document #: 38-03036 Rev. **
SU
AS1
CC
) is the lowest frequency. The lowest of these frequencies
SU
or GND). Each set of V
if all inputs are on dedicated input pins.
. Determine which of 1/(t
AWH
OH
+ t
is greater than the minimum required input hold
AWL
EXP
OH
), 1/t
to the overall delay.
indicates the system compatibility of this
ACO1
CC
, or 1/(t
and GND pins must be connect-
(V
WH
IN
EXP
+ t
EXP
or V
WL
to t
), 1/t
OUT
AS1
+ t
AS1
. Determine which
)
CO1
) is the lowest
V
, or 1/(t
CC
SU
. Unused
if all in-
CC
EXP
EXP
pin
CC
+
Typical I
Output Drive Current
250
240
180
120
60
200
150
100
50
100 Hz
CC
0
0
vs. f
1 kHz
V
1
O
MAXIMUM FREQUENCY
MAX
V
Room Temp.
OUTPUT VOLTAGE (V)
CC
10 kHz
=5.0V
I
OL
2
100 kHz 1 MHz
V
Room Temp.
I
CC
3
OH
=5.0V
4
10 MHz
CY7C344B
Page 3 of 12
C344B–9
50 MHz
C344B–8
5