CS42428-CQZ Cirrus Logic Inc, CS42428-CQZ Datasheet

IC CODEC 8CH PLL 192KHZ 64-LQFP

CS42428-CQZ

Manufacturer Part Number
CS42428-CQZ
Description
IC CODEC 8CH PLL 192KHZ 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42428-CQZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
15
Adc / Dac Resolution
24bit
Sampling Rate
192kSPS
Ic Interface Type
I2C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1499 - BOARD EVAL FOR CS42428 CODEC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1031

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42428-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
135
Part Number:
CS42428-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42428-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Features
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Eight 24-bit D/A, two 24-bit A/D Converters
114 dB DAC / 114 dB ADC Dynamic Range
-100 dB THD+N
System Sampling Rates up to 192 kHz
Integrated Low-Jitter PLL for Increased System
Jitter Tolerance
PLL Clock or System Clock Selection
7 Configurable General-Purpose Outputs
ADC High-Pass Filter for DC Offset Calibration
Expandable ADC Channels and One-Line
Mode Support
Digital Output Volume Control with Soft Ramp
Digital +/-15 dB Input Gain Adjust for ADC
Differential Analog Architecture
Supports Logic Levels between 1.8 V and 5 V
http://www.cirrus.com
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
MUTEC
AINL+
AINL-
AINR+
AINR-
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
114 dB, 192 kHz 8-Ch Codec with PLL
VA AGND
GPO
ADC#1
ADC#2
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
Mute
Digital Filter
Digital Filter
REFGND VQ
Copyright © Cirrus Logic, Inc. 2005
Internal Voltage
Reference
(All Rights Reserved)
FILT+
Gain & Clip
Gain & Clip
General Description
The CS42428 codec provides two analog-to-digital and
eight digital-to-analog delta-sigma converters, as well
as an integrated PLL.
The CS42428 integrated PLL provides a low-jitter sys-
tem clock. The internal stereo ADC is capable of
independent channel gain control for single-ended or
differential analog inputs. All eight channels of DAC pro-
vide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute con-
trols or ADC overflow indicators.
The CS42428 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, digital speaker and
automotive audio systems.
The CS42428 is available in a 64-pin LQFP package in
both Commercial (-10° to 70° C) and Automotive
(-40° to 85° C) grades. The CDB42428 Customer Dem-
onstration board is also available for device evaluation.
Refer to
OMCK
PLL
Serial
Audio
“Ordering Information” on page
ADC
Port
Mult/Div
RMCK LPFLT
Control
VLC
Port
DGND VD
CS42428
INT
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
ADCIN1
ADCIN2
ADC_SDOUT
ADC_LRCK
ADC_SCLK
VLS
DAC_LRCK
DAC_SCLK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
NOVEMBER '05
71.
DS605F1

Related parts for CS42428-CQZ

CS42428-CQZ Summary of contents

Page 1

... A/V receivers, DVD receivers, digital speaker and automotive audio systems. The CS42428 is available in a 64-pin LQFP package in both Commercial (-10° to 70° C) and Automotive (-40° to 85° C) grades. The CDB42428 Customer Dem- onstration board is also available for device evaluation. ...

Page 2

... Memory Address Pointer (MAP) ..................................................................................................... 42 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42 6.3 Power Control (address 02h) .......................................................................................................... 43 6.4 Functional Mode (address 03h) ...................................................................................................... 43 6.5 Interface Formats (address 04h) .................................................................................................... 45 6.6 Misc Control (address 05h) ............................................................................................................ 46 2 ™ FORMAT .......................................... 13 .............................................................................................. 18 CS42428 DS605F1 ...

Page 3

... Figure 9.ATAPI Block Diagram (x = channel pair ..................................................................... 22 Figure 10.Clock Generation ...................................................................................................................... 23 Figure 11.Right-Justified Serial Audio Formats ......................................................................................... 27 Figure 12.I²S Serial Audio Formats ........................................................................................................... 28 Figure 13.Left-Justified Serial Audio Formats ........................................................................................... 28 Figure 14.One Line Mode #1 Serial Audio Format .................................................................................... 29 Figure 15.One Line Mode #2 Serial Audio Format .................................................................................... 29 DS605F1 ............................................................................................................... 70 CS42428 ...................................... 53 3 ...

Page 4

... Figure 55.Quad-Speed (fast) Stopband Rejection .................................................................................... 68 Figure 56.Quad-Speed (fast) Transition Band .......................................................................................... 68 Figure 57.Quad-Speed (fast) Transition Band (detail) .............................................................................. 69 Figure 58.Quad-Speed (fast) Passband Ripple ........................................................................................ 69 Figure 59.Quad-Speed (slow) Stopband Rejection ................................................................................... 69 Figure 60.Quad-Speed (slow) Transition Band ......................................................................................... 69 Figure 61.Quad-Speed (slow) Transition Band (detail) ............................................................................. 69 Figure 62.Quad-Speed (slow) Passband Ripple ....................................................................................... 69 4 CS42428 DS605F1 ...

Page 5

... Table 8. DAC One-Line Mode.................................................................................................................... 45 Table 9. RMCK Divider Settings ................................................................................................................ 48 Table 10. OMCK Frequency Settings ........................................................................................................ 48 Table 11. Master Clock Source Select....................................................................................................... 49 Table 12. PLL Clock Frequency Detection................................................................................................. 50 Table 13. Example Digital Volume Settings ............................................................................................... 53 Table 14. ATAPI Decode ........................................................................................................................... 54 Table 15. Example ADC Input Gain Settings ............................................................................................. 55 Table 16. PLL External Component Values ............................................................................................... 62 DS605F1 CS42428 5 ...

Page 6

... T A CS42428-DQZ Symbol Analog VA Digital VD Serial Port Interface VLS Control Port Interface VLC (Note (Note Serial Port Interface V IND-S Control Port Interface V IND-C CS42428-CQZ T A CS42428-DQZ stg CS42428 Min Typ Max Units 4.75 5.0 5.25 V 3.13 3.3 5.25 V 1.8 5.0 5. ...

Page 7

... Offset Error HPF_FREEZE disabled HPF_FREEZE enabled Analog Input Full-scale Differential Input Voltage Input Impedance (Differential) (Note 4) Common Mode Rejection Ratio Notes: 3. Referred to the typical full-scale voltage. 4. Measured between AIN+ and AIN- DS605F1 CS42428-CQZ Symbol Min Typ Max 108 114 - 105 111 - - ...

Page 8

... Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. 8 Symbol Min Typ (Note (Note 5) 0. 12/Fs gd ∆ (Note (Note 5) 0. 9/Fs gd ∆ (Note (Note 5) 0. 5/Fs gd ∆ (Note 6) 20 (Note /Fs CS42428 Max Unit 0.47 Fs ±0.035 µs 0.0 0.45 Fs ±0.035 µs 0.0 0.24 Fs ±0.035 µs 0 Deg DS605F1 ...

Page 9

... Analog Output Characteristics for all modes Unloaded Full-Scale Differential Output Voltage Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance Notes: 7. One-half LSB of triangular PDF dither is added to data. 8. Performance limited by 16-bit quantization noise. DS605F1 CS42428-CQZ Symbol Min Typ Max 108 114 - 105 111 - - ...

Page 10

... kHz - - Fs = 44.1 kHz - - kHz - - -0.01 - 0.5834 - (Note 10 4.6/ kHz - - ±0.03/ -0.01 - 0.6355 - (Note 10 4.7/ kHz - - ±0.01/Fs CS42428 Slow Roll-Off Max Min Typ Max 0.4535 0 - 0.4166 0.4998 0 - 0.4998 +0.01 -0.01 - +0.01 - 0.5834 - - - 6.5/ ±0.14/Fs ±0. ±0.23 ±0. ±0.14 ±0. ±0.09 0.4166 ...

Page 11

... DAC_SCLK, ADC_SCLK Low Time DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK Edge Notes: 12. After powering-up the CS42428, RST should be held low after the power supplies and clocks are set- tled. 13. See Table 1 on page 24 14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz. ...

Page 12

... Double-Speed Mode, × 128 Fs t high t sud t ack t hdd Figure 3. Control Port Timing - I²C Format CS42428 Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µ ...

Page 13

... CCLK CDIN CDOUT DS605F1 = -40 to +85° =VLS= 3.3 V; VLC = 1 5. pF) L Symbol f sck t csh t css t scl t sch t dsu (Note 20 (Note 21 (Note 21 scl t sch t css dsu Figure 4. Control Port Timing - SPI Format CS42428 ™ FORMAT Min Typ Max Units 0 - 6.0 MHz µs 1 ...

Page 14

... Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5. 14 Symbol normal operation 3 (Note 23 VLS (Note 24 (Note 22) normal operation power-down (Note 24) normal operation power-down (Note 24) (1 kHz) PSRR (60 Hz) CS42428 Min Typ Max Units - µA - 250 - - µA - 250 - - 587 ...

Page 15

... When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load. DS605F1 = -40 to +85° Symbol Serial Port Control Port V IH Serial Port Control Port V IL (Note 27)Serial Port Control Port V OH MUTEC, GPOx (Note 27 CS42428 Min Typ Max Units 0.7xVLS - - 0.7xVLC - - - - 0.2xVLS - - 0.2xVLC VLS-1 VLC-1 VA-1.0 ...

Page 16

... Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode AD0/CS is the chip select signal in SPI mode. Interrupt (Output) - The CS42428 will generate an interrupt condition as per the Interrupt Mask register. 11 INT See “Interrupts” on page 37 ...

Page 17

... ADC Serial Data Output (Output) - Output for two’s complement serial audio PCM data from the output 56 ADC_SDOUT of the internal and external ADCs. External ADC Serial Input (Input) - The CS42428 provides for up to two external stereo analog to digital 58 ADCIN1 converter inputs to provide a maximum of six channels on one serial data output line when the CS42428 ...

Page 18

... REFGND VLC 0.1 µF LPFLT DGND DGND AGND AGND Connect DGND and AGND at single point near Codec Figure 5. Typical Connection Diagram CS42428 +5 V 0.01 µF 0.1 µ µF 0.01 µF 0.1 µ µ Analog Output Buffer and 37 Mute Circuit (optional) ...

Page 19

... CS42428 Ω µ CS42428 + µ µ µ µ µ µ ffe irc tio ffe irc tio ffe irc tio ffe irc tio ffe irc tio ffe irc tio ffe irc tio ffe irc tio riv ire tio rtu tro ...

Page 20

... CS42428. The CS42428 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM bits in register (SSM) supports input sample rates kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x ...

Page 21

... This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS42428 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset. ...

Page 22

... Each pin can be programmed as an output, with specific muting capabilities as defined by the function bits in the register “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 4.3.4 ATAPI Specification The CS42428 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to mation. Left Channel Audio Data ...

Page 23

... Clock Generation The clock generation for the CS42428 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input ...

Page 24

... PLL Output (MHz) Single-Speed Double-Speed (4 to 50kHz) (50 to 100kHz) 256x 256x 8.1920 - 11.2896 - 12.2880 - - 16.3840 - 22.5792 - 24.5760 - - - - CS42428 “Clock Con- must be applied to the OMCK pin at all times 49). Quad-Speed (100 to 192 kHz) 64x 96x 128x - - - - - - - - 12.2880 18.4320 24.5760 Quad-Speed (100 to 192kHz) 256x - - ...

Page 25

... DAC_SP M/S and ADC_SP M/S in register The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS42428 (Master Mode may be generated by an external source (Slave Mode). As described in later sections, particular modes of operation do allow the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other. The serial data interface format selection (Left/Right-Justified, I² ...

Page 26

... DAC #7 right channel DAC #8 one line mode DAC channels 7,8 left channel ADC #1 right channel ADC #2 One-Line Mode ADC channels 1,2,3,4,5,6 left channel External ADC #3 right channel External ADC #4 left channel External ADC #5 right channel External ADC #6 CS42428 DS605F1 ...

Page 27

... These formats are selected using the configuration bits in the registers, and “Interface Formats (address 04h)” on page SCLK Rate(s) Slave 48, 64, 128 Fs Single-Speed Mode 64 Fs Double-Speed Mode 64 Fs Quad-Speed Mode 64, 128 Fs Single-Speed Mode 64 Fs Double-Speed Mode 64 Fs Quad-Speed Mode CS42428 45. For the R igh t C han nel Notes 27 ...

Page 28

... Figure 12. I²S Serial Audio Formats + LSB MSB SCLK Rate(s) Slave 32, 48, 64, 128 Fs Single-Speed Mode 32 Double-Speed Mode 32 Quad-Speed Mode 48, 64, 128 Fs Single-Speed Mode 64 Fs Double-Speed Mode 64 Fs Quad-Speed Mode Figure 13. Left-Justified Serial Audio Formats CS42428 Rig nnel - LSB Notes R ight C hannel - LSB Notes DS605F1 ...

Page 29

... AC5 DAC2 24 clks 24 clks D AC8 24 clks A DC5 A DC2 24 clks 24 clks SCLK Rate(s) Slave not supported single-speed mode CS42428 64 clks Right C hannel LSB LSB D AC4 D AC6 20 clks 20 clks A DC4 A DC6 20 clks 20 clks Notes 128 clks Right C hannel ...

Page 30

... Figure 16. ADCIN1/ADCIN2 Serial Audio Format For proper operation, the CS42428 must be configured to select which SCLK/LRCK is being used to clock the external ADCs. The EXT ADC SCLK bit in register set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs are wired to use the ADC_SP clocks, set this bit to ‘ ...

Page 31

... MCLK RMCK ADCIN1 64Fs,128Fs, 256Fs DAC_SCLK ADCIN2 DAC_LRCK ADC Data ADC_SDOUT DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 CS42428 Figure 17. OLM Configuration #1 CS42428 Description One-Line Mode #2 not valid not valid DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK M CLK SCLK_PO RT1 LRCK_PO RT1 SDIN_PORT1 SCLK_PO RT2 LRCK_PO RT2 ...

Page 32

... ADC_SCLK ADC_LRCK ADC Data RMCK ADC_SDOUT ADCIN1 ADCIN2 64Fs,128Fs DAC_SCLK DAC_LRCK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 CS42428 Figure 18. OLM Configuration #2 CS42428 Description One-Line Mode #2 not valid not valid not valid M CLK SCLK_PORT1 LRCK_PORT1 SDIN_PORT1 SCLK_PORT2 LRCK_PORT2 SDOUT1_PORT2 SDOUT2_PORT2 SDOUT3_PORT2 SDOUT4_PORT2 DIGITAL AUDIO ...

Page 33

... LRCK ADC_SCLK SCLK ADC_LRCK MCLK RMCK ADC_SDOUT ADCIN1 ADCIN2 64Fs,128Fs,256Fs DAC_SCLK DAC_LRCK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 CS42428 Figure 19. OLM Configuration #3 CS42428 Description One-Line Mode #2 DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=128Fs ADC_LRCK=SSM not valid MCLK SCLK_PORT1 LRCK_PORT1 SDIN_PORT1 SCLK_PORT2 LRCK_PORT2 SDOUT1_PORT2 ...

Page 34

... ADCIN1 ADCIN2 SDIN_PORT2 64Fs,128Fs, 256Fs SCLK_PORT2 DAC_SCLK LRCK_PORT2 DAC_LRCK SDOUT1_PORT2 DAC_SDIN1 DAC_SDIN2 SDOUT2_PORT2 DAC_SDIN3 SDOUT3_PORT2 DAC_SDIN4 SDOUT4_PORT2 DIGITAL AUDIO CS42428 PROCESSOR Figure 20. OLM Configuration #4 CS42428 Description clocks. ADC are supported One-Line Mode #2 DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs/128Fs ADC_LRCK=SSM/DSM/QSM not valid not valid DS605F1 ...

Page 35

... The control port has two modes: SPI and I²C, with the CS42428 acting as a slave device. SPI mode is se- lected if there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state ...

Page 36

... CS42428 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42428, the chip address field, which is the first byte sent to the CS42428, should match 10011, followed by the settings of the AD1 and AD0 ...

Page 37

... When RST is low, the CS42428 enters a low-power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes opera- tional, and the desired settings should be loaded into the control registers ...

Page 38

... The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42428 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µ ...

Page 39

... Reserved Reserved Reserved SZC1 SZC0 AMUTE B3_MUTE A3_MUTE B2_MUTE A1_VOL5 A1_VOL4 A1_VOL3 B1_VOL5 B1_VOL4 B1_VOL3 A2_VOL5 A2_VOL4 A2_VOL3 B2_VOL5 B2_VOL4 B2_VOL3 CS42428 Rev_ID2 Rev_ID1 Rev_ID0 PDN_DAC2 PDN_DAC1 ADC_CLK DAC_DEM Reserved SEL DAC_OL0 Reserved CODEC_RJ16 HPF_ DAC_SP ADC_SP FREEZE M SW_CTRL1 SW_CTRL0 FRC_PLL_LK ...

Page 40

... LGAIN4 LGAIN3 RGAIN5 RGAIN4 RGAIN3 DE-EMPH1 DE-EMPH0 INT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CS42428 A3_VOL2 A3_VOL1 A3_VOL0 B3_VOL2 B3_VOL1 B3_VOL0 A4_VOL2 A4_VOL1 A4_VOL0 B4_VOL2 B4_VOL1 B4_VOL0 INV_A2 INV_B1 INV_A1 P1_ATAPI2 P1_ATAPI1 P1_ATAPI0 P2_ATAPI2 P2_ATAPI1 ...

Page 41

... Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 CS42428 Reserved OF0 Reserved Reserved Reserved Reserved M_AOUTA3 M_AOUTA4 M_AOUTB2 M_AOUTB3 M_AOUTB4 Function2 Function1 Function0 Function2 Function1 Function0 Function2 Function1 Function0 0 0 ...

Page 42

... Chip I.D. and Revision Register (address 01h) (Read Only Chip_ID3 Chip_ID2 Chip_ID1 6.2.1 CHIP I.D. (CHIP_IDX) Default = 1111 Function: I.D. code for the CS42428. Permanently set to 1111. 6.2.2 CHIP REVISION (REV_IDX) Default = xxxx Function: CS42428 revision level. Revision C1 is coded as 0101 Revision C is coded as 0011 ...

Page 43

... Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP). Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave Mode. DS605F1 PDN_DAC4 PDN_DAC3 ADC_FM0 Reserved CS42428 2 1 PDN_DAC2 PDN_DAC1 PDN 2 1 ADC_SP SEL DAC_DEM Reserved 0 0 ...

Page 44

... To apply the correct de-emphasis filter, use the DE-EMPH bits in the Interrupt Control (address 1Eh) register to set the appropriate sample rate. DAC_DEM reg03h[ FRC_PLL_LK DE-EMPH[1:0] reg06h[0] reg1Eh[5: Table 5. DAC De-Emphasis CS42428 De-Emphasis Mode No De-Emphasis Auto-Detect Fs Reserved 32 kHz 44.1 kHz 48 kHz DS605F1 ...

Page 45

... Description DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2 Reserved Table 7. ADC One-Line Mode 14 and 15 Description DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2 Reserved Table 8. DAC One-Line Mode CS42428 2 1 DAC_OL0 Reserved CODEC_RJ16 Figures 11-13. Format Figure ...

Page 46

... FREEZE is disabled. To make multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit FREEZE FILT_SEL CS42428 2 1 HPF_FREEZE DAC_SP ADC_SP M/S M/S DS605F1 ...

Page 47

... To use the PLL to lock to ADC_LRCK, the ADC_SP must be in Slave Mode. When using the PLL to lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, both ADC_SCLK and ADC_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, only the ADC_LRCK signal must be applied. DS605F1 “D/A Digital Filter Characteristics” on page 8. CS42428 10. “A/D Dig- 47 ...

Page 48

... OMCK Freq1 OMCK Freq0 6.7.3 PLL LOCK TO LRCK (PLL_LRCK) Default = Disabled 1 - Enabled Function: When enabled, the internal PLL of the CS42428 will lock to the ADC_LRCK of the ADC serial port (ADC_LRCK) while the ADC_SP is in Slave Mode OMCK Freq0 PLL_LRCK Description 0 0 Divide by 1 ...

Page 49

... These two bits, along with the UNLOCK bit in register on page 56, determine the master clock source for the CS42428. When SW_CTRL1 and SW_CTRL0 are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid. ...

Page 50

... PLL CLOCK FREQUENCY (PLL_CLKX) Default = xxx Function: The CS42428 detects the ratio between the OMCK and the recovered clock from the PLL. Given the absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL clock 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX ...

Page 51

... The zero cross function is independently monitored and implemented for each channel. DS605F1 SZC0 AMUTE CS42428 MUTE RAMP_UP RAMP_DN ADC_SP 51 ...

Page 52

... Enabled Function: The digital-to-analog converters of the CS42428 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the MUTEC pin will go active during the mute period ...

Page 53

... Control registers are ignored when this function is enabled. DS605F1 xx_VOL4 xx_VOL3 Decimal Value 120 180 Table 13. Example Digital Volume Settings INV_A3 INV_B2 Px_ATAPI4 Px_ATAPI3 CS42428 2 1 xx_VOL2 xx_VOL1 xx_VOL0 Table 13. The volume changes Volume Setting 0 dB -20 dB -40 dB - INV_A2 INV_B1 INV_A1 2 1 Px_ATAPI2 Px_ATAPI1 Px_ATAPI0 ...

Page 54

... ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42428 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 Table 14 ATAPI1 ATAPI0 AOUTAx MUTE MUTE MUTE MUTE a[(L+R)/ a[(L+R)/2] ...

Page 55

... DS605F1 LGAIN4 LGAIN3 RGAIN4 RGAIN3 Decimal Value +15 + -10 -15 Table 15. Example ADC Input Gain Settings DE-EMPH0 INT1 CS42428 2 1 LGAIN2 LGAIN1 LGAIN0 2 1 RGAIN2 RGAIN1 RGAIN0 Volume Setting + - INT0 Reserved Reserved ...

Page 56

... PLL UNLOCK (UNLOCK) Default = 0 Function: PLL unlock status bit. This bit will go high if the PLL becomes unlocked. 6.18.2 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42428 ADC signal path Reserved Reserved CS42428 “ ...

Page 57

... Function: Determines the polarity of the MUTEC pin. DS605F1 Reserved Reserved 56 mask bit is set to 1, the error is unmasked, meaning that Reserved Reserved Reserved Reserved 55 M_AOUTA1 M_AOUTB1 CS42428 Reserved OverFlowM Reserved “Interrupt Status Reserved OF1 Reserved Reserved OF0 Reserved “Interrupt Control M_AOUTA2 M_AOUTA3 ...

Page 58

... Mode pin, the polarity bit is ignored recommended that in this mode this bit be set to 0. GPO, Drive High - If the pin is configured as a general-purpose output driven high, the polarity bit is ignored recommended that in this mode this bit be set Function4 Function3 CS42428 Function2 Function1 Function0 DS605F1 ...

Page 59

... M_AOUTB2 M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTB3 M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTB3 Function0 GPOx 0 0 Drive Low 1 1 OVFL CS42428 Function1 Function0 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA4 M_AOUTB3 M_AOUTB4 ...

Page 60

... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 60 CS42428 DS605F1 ...

Page 61

... DAC Output Filter The CS42428 is a linear phase design and does not include phase or amplitude compensation for an exter- nal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external an- alog circuitry. AOUT - AOUT + Figure 25. Recommended Analog Output Buffer DS605F1 Ω ...

Page 62

... Avoid capacitors with large temperature co-coefficient, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics. 62 RFILT (kΩ) CFILT (µF) CRIP (pF) 2.55 0.047 2200 Table 16. PLL External Component Values CS42428 Table 16 have a high corner-frequen- DS605F1 ...

Page 63

... The traces themselves are short to minimize the inductance in the filter path. The VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing. DS605F1 0.01 µF CRIP 0.1 µF CFILT 10 µF = via to ground plane Figure 26. Recommended Layout Example CS42428 63 ...

Page 64

... Figure 32. Double-Speed Mode Transition Band CS42428 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Frequency (normalized to Fs) 0.48 ...

Page 65

... Figure 38. Quad-Speed Mode Passband Ripple CS42428 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 Frequency (normalized to Fs) 0 ...

Page 66

... Figure 42. Single-Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 44. Single-Speed (slow) Transition Band CS42428 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) ...

Page 67

... Figure 48. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 50. Double-Speed (fast) Passband Ripple CS42428 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...

Page 68

... Figure 54. Double-Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 56. Quad-Speed (fast) Transition Band CS42428 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...

Page 69

... Figure 60. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 62. Quad-Speed (slow) Passband Ripple CS42428 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...

Page 70

... BSC 0.484 0.393 BSC 0.398 0.472 BSC 0.484 0.393 BSC 0.398 0.020 BSC 0.024 0.024 0.030 4° 7.000° Symbol θ CS42428 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.20 0.27 11.70 12.0 BSC 12 ...

Page 71

... Philips Semiconductor, The I2C-Bus Specification: Version 2.1, January 2000. ductors.philips.com DS605F1 Package Pb-Free Grade Commercial -10° to +70° C 64-pin YES LQFP Automotive -40° to +85° CS42428 Temp Range Container Order # CS42428-CQZ Tray Tape & Reel CS42428-CQZR Tray CS42428-DQZ Tape & Reel CS42428-DQZR CDB42428 - - http://www.semicon- 71 ...

Page 72

... Updated section 4.4.4 on page – Corrected default value of the Chip_ID[3:0] bits in register 01h on pages 39 and 42. – Updated default value of the Rev_ID[3:0] bits in register 01h on pages and 42. – Updated PLL_CLK[2:0] bit description on CS42428 page 71. on page 47. on page 49. 62. page 7. page , t , and t ...

Page 73

... AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. DS605F1 www.cirrus.com/corporate/contacts/sales.cfm CS42428 73 ...

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