CS42528-DQZ Cirrus Logic Inc, CS42528-DQZ Datasheet

IC CODEC S/PDIF RCVR 64-LQFP

CS42528-DQZ

Manufacturer Part Number
CS42528-DQZ
Description
IC CODEC S/PDIF RCVR 64-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42528-DQZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
114dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42528-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42528-DQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Features
Eight 24-bit D/A, two 24-bit A/D Converters
114 dB DAC / 114 dB ADC Dynamic Range
-100 dB THD+N
System Sampling Rates up to 192 kHz
S/PDIF Receiver Compatible with EIAJ
CP1201 and IEC-60958
Recovered S/PDIF Clock or System Clock
Selection
8:2 S/PDIF Input MUX
ADC High-Pass Filter for DC Offset Calibration
Expandable ADC Channels and One-Line
Mode Support
Digital Output Volume Control with Soft Ramp
Digital +/-15 dB Input Gain Adjust for ADC
Differential Analog Architecture
Supports Logic Levels between 1.8 V and 5 V
http://www.cirrus.com
114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
REFGND
MUTEC
AINR+
AGND
AINL+
AINR-
RXP0
FILT+
AINL-
VQ
VA
Ref
ADC#1
ADC#2
TXP
Rx
MUTE
GPO
VARX
Clock/Data
AGND
Recovery
Digital Filter
Digital Filter
Copyright © Cirrus Logic, Inc. 2005
DAC#4
DAC#5
DAC#6
LPFLT
DAC#1
DAC#2
DAC#3
DAC#7
DAC#8
(All Rights Reserved)
Decoder
Gain & Clip
S/PDIF
Gain & Clip
DEM
General Description
The CS42528 codec provides two analog-to-digital and
eight digital-to-analog delta-sigma converters, as well
as an integrated S/PDIF receiver.
The CS42528 integrated S/PDIF receiver supports up
to eight inputs, clock recovery circuitry and format auto-
detection. The internal stereo ADC is capable of inde-
pendent channel gain control for single-ended or
differential analog inputs. All eight channels of DAC pro-
vide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute con-
trols or ADC overflow indicators.
The CS42528 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, digital speaker and
automotive audio systems.
The CS42528 is available in a 64-pin LQFP package in
both Commercial (-10° to 70° C) and Automotive
(-40° to 85° C) grades. The CDB42528 Customer Dem-
onstration board is also available for device evaluation.
Refer to
DGND
Data Buffer
C&U Bit
Detector
Format
Serial
ADC
Data
Internal MCLK
DGND VD
“Ordering Information” on page
VD
Interface
Mult/Div
Control
CODEC
Serial
Audio
Serial
Port
Port
Port
INT
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OMCK
RMCK
SAI_LRCK
SAI_SCLK
SAI_SDOUT
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CS42528
NOVEMBER '05
89.
DS586F1

Related parts for CS42528-DQZ

CS42528-DQZ Summary of contents

Page 1

... A/V receivers, DVD receivers, digital speaker and automotive audio systems. The CS42528 is available in a 64-pin LQFP package in both Commercial (-10° to 70° C) and Automotive (-40° to 85° C) grades. The CDB42528 Customer Dem- onstration board is also available for device evaluation. ...

Page 2

... OLM Config #4 ........................................................................................................... 36 4.6.4.5 OLM Config #5 ........................................................................................................... 37 4.7 Control Port Description and Timing ............................................................................................... 38 4.7.1 SPI Mode ............................................................................................................................... 38 4.7.2 I²C Mode ................................................................................................................................ 39 4.8 Interrupts ........................................................................................................................................ 40 4.9 Reset and Power-Up ...................................................................................................................... 40 4.10 Power Supply, Grounding, and PCB Layout ................................................................................ 41 5. REGISTER QUICK REFERENCE ........................................................................................................ 42 2 ™ FORMAT .......................................... 14 ............................................................................................... 20 CS42528 DS586F1 ...

Page 3

... One-Byte Mode .......................................................................................................... 75 9.2.1.2 Two-Byte Mode .......................................................................................................... 75 9.2.2 Serial Copy Management System (SCMS) ........................................................................... 76 9.3 User (U) Data E Buffer Access ....................................................................................................... 76 9.3.1 Non-Audio Auto-Detection ..................................................................................................... 76 9.3.1.1 Format Detection ....................................................................................................... 76 10. APPENDIX C: PLL FILTER ................................................................................................................ 77 10.1 External Filter Components .......................................................................................................... 77 10.1.1 General ................................................................................................................................ 77 10.1.2 Jitter Attenuation ................................................................................................................. 79 10.1.3 Capacitor Selection ............................................................................................................. 80 DS586F1 CS42528 ...................................... 58 3 ...

Page 4

... Figure 5.Typical Connection Diagram ....................................................................................................... 20 Figure 6.Full-Scale Analog Input ............................................................................................................... 21 Figure 7.Full-Scale Output ........................................................................................................................ 22 Figure 8.ATAPI Block Diagram (x = channel pair ..................................................................... 23 Figure 9.CS42528 Clock Generation ........................................................................................................ 25 Figure 10.I²S Serial Audio Formats ........................................................................................................... 29 Figure 11.Left-Justified Serial Audio Formats ........................................................................................... 30 Figure 12.Right-Justified Serial Audio Formats ......................................................................................... 30 Figure 13.One-Line Mode #1 Serial Audio Format ................................................................................... 31 Figure 14 ...

Page 5

... Figure 62.Quad-Speed (fast) Stopband Rejection .................................................................................... 86 Figure 63.Quad-Speed (fast) Transition Band .......................................................................................... 86 Figure 64.Quad-Speed (fast) Transition Band (detail) .............................................................................. 87 Figure 65.Quad-Speed (fast) Passband Ripple ........................................................................................ 87 Figure 66.Quad-Speed (slow) Stopband Rejection ................................................................................... 87 Figure 67.Quad-Speed (slow) Transition Band ......................................................................................... 87 Figure 68.Quad-Speed (slow) Transition Band (detail) ............................................................................. 87 Figure 69.Quad-Speed (slow) Passband Ripple ....................................................................................... 87 DS586F1 CS42528 5 ...

Page 6

... Table 14. Receiver Clock Frequency Detection......................................................................................... 56 Table 15. Example Digital Volume Settings ............................................................................................... 58 Table 16. ATAPI Decode ........................................................................................................................... 60 Table 17. Example ADC Input Gain Settings ............................................................................................. 61 Table 18. TXP Output Selection................................................................................................................. 63 Table 19. Receiver Input Selection ............................................................................................................ 63 Table 20. Auxiliary Data Width Selection ................................................................................................... 66 Table 21. External PLL Component Values & Locking Modes .................................................................. 77 6 CS42528 DS586F1 ...

Page 7

... Serial Port Interface VLS Control Port Interface VLC (Note (Note 2) IN Serial Port Interface V IND-S Control Port Interface V IND-C S/PDIF interface V IND-SP CS42528-CQZ T A CS42528-DQZ stg CS42528 Min Typ Max Units 4.75 5.0 5.25 V 3.13 3.3 5.25 V 1.8 5.0 5.25 V 1.8 5 ...

Page 8

... THD -97 - 108 114 - 105 111 - - 108 - - -100 -94 THD 110 - - 0.0001 - - 0 +/-100 - - 100 - 1.05 VA 1. CMRR - 82 - CS42528 CS42528-DQZ Min Typ Max Unit 106 114 - dB 103 111 - dB - -100 - - - 106 114 - dB 103 111 - dB - 108 - dB - -100 - - - - 106 114 - dB 103 111 - dB - 108 - dB - -100 ...

Page 9

... Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DS586F1 Symbol Min Typ (Note (Note 5) 0. 12/Fs gd ∆ (Note (Note 5) 0. 9/Fs gd ∆ (Note (Note 5) 0. 5/Fs gd ∆ (Note 6) 20 (Note /Fs CS42528 Max Unit 0.47 Fs ±0.035 µs 0.0 0.45 Fs ±0.035 µs 0.0 0.24 Fs ±0.035 µs 0 Deg ...

Page 10

... Performance limited by 16-bit quantization noise. 10 CS42528-CQZ Symbol Min Typ Max 108 114 - 105 111 - - -100 -94 - -91 - THD -34 - 114 - - .89 VA . 300 - Z - 150 - OUT CS42528 L CS42528-DQZ Min Typ Max Unit 106 114 - dB 103 111 - -100 - - - - - - 114 - .84 VA .94 VA 1.04 VA Vpp - 0 300 - ppm/°C Ω - 150 - kΩ ...

Page 11

... kHz - - Fs = 44.1 kHz - - kHz - - -0.01 - 0.5834 - (Note 10 4.6/ kHz - - ±0.03/ -0.01 - 0.6355 - (Note 10 4.7/ kHz - - ±0.01/Fs CS42528 Slow Roll-Off Max Min Typ Max 0.4535 0 - 0.4166 0.4998 0 - 0.4998 +0.01 -0.01 - +0.01 - 0.5834 - - - 6.5/ ±0.14/Fs ±0. ±0.23 ±0. ±0.14 ±0. ±0.09 0.4166 ...

Page 12

... CX_SCLK, SAI_SCLK Low Time CX_SCLK, SAI_SCLK falling to CX_LRCK, SAI_LRCK Edge Notes: 12. After powering-up the CS42528, RST should be held low after the power supplies and clocks are set- tled. 13. See Table 1 on page 26 14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz. ...

Page 13

... Double-Speed Mode, × 128 Fs t high t sud t ack t hdd Figure 3. Control Port Timing - I²C Format CS42528 Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µ ...

Page 14

... CDOUT 14 = -40 to +85° C; VA=VARX = =VLS= 3.3 V; VLC = 1 pF) L Symbol (Note 20) f sck t csh t css t scl t sch t dsu (Note 21 (Note 22 (Note 22 scl t sch t css dsu Figure 4. Control Port Timing - SPI Format CS42528 ™ FORMAT Min Typ Max Units 0 - 6.0 MHz µ ...

Page 15

... Power-Down Mode is defined as RST pin = Low with all clock and data lines held static. 26. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5. DS586F1 Symbol 3 (Note 24 VLS (Note 25 (Note 23) normal operation power-down (Note 25) normal operation power-down (Note 25) (1 kHz) PSRR (60 Hz) CS42528 Min Typ Max Units - µ 250 - - µ 250 - - 587 ...

Page 16

... When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load -40 to +85° Symbol Serial Port Control Port V IH Serial Port Control Port V IL (Note 28)Serial Port Control Port MUTEC, GPOx V OH TXP (Note 28 CS42528 Min Typ Max Units 0.7xVLS - - 0.7xVLC - - - - 0.2xVLS - - 0.2xVLC VLS-1 VLC-1 VA-1 VD-1.0 ...

Page 17

... SPI mode. Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input ) - AD0 is a chip address pin in I²C mode AD0/CS is the chip select signal in SPI mode. DS586F1 CS42528 CS42528 ...

Page 18

... CODEC Serial Data Output ( Output ) - Output for two’s complement serial audio data from the internal 56 CX_SDOUT and external ADCs. External ADC Serial Input ( Input ) - The CS42528 provides for up to two external stereo analog to digital 58 ADCIN1 converter inputs to provide a maximum of six channels on one serial data output line when the CS42528 ...

Page 19

... Frequency (OMCK Freqx)” on page Serial Audio Interface Left/Right Clock ( Input / Output ) - Determines which channel, Left or Right SAI_LRCK currently active on the serial audio data line. SAI_SCLK 61 Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface. DS586F1 CS42528 53. 19 ...

Page 20

... ILT + ** ect gle p oin Figure 5. Typical Connection Diagram CS42528 +5 V 0.01 µ F 0.1 µ µ F 0.01 µ F 0.1 µ µ nalog O utput B uffer and 37 M ute C irc uit (optional nalog O utput B uffer 34 and M ute C irc uit (optional nalog O utput B uffer ...

Page 21

... I²C mode. Figure 5 shows the recommended connections for the CS42528. The CS42528 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM bits in register (SSM) supports input sample rates kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x ...

Page 22

... This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS42528 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset. ...

Page 23

... ATAPI Specification The CS42528 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to mation. Left Channel Audio Data ...

Page 24

... S/PDIF Input Multiplexer The CS42528 contains an 8:2 S/PDIF Input Multiplexer to accommodate up to eight channels of input dig- ital audio data. Digital audio data is single-ended and input through the RXP0 and RXP1/GPO1-RXP7/GPO7 pins. Any one of these inputs can be multiplexed to the input of the S/PDIF receiver and to the S/PDIF output pin TXP ...

Page 25

... Clock Generation The clock generation for the CS42528 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input ...

Page 26

... Double Speed ( kHz) (50 to 100 kHz) 256x 256x 8.1920 - 11.2896 - 12.2880 - - 16.3840 - 22.5792 - 24.5760 - - - - CS42528 “Clock Con- must be applied to the OMCK pin at all times 54). Quad-Speed (100 to 192 kHz) 64x 96x 128x - - - - - - - - 12.2880 18.4320 24.5760 “Clock Control (address 06h)” below. Quad Speed ...

Page 27

... CODEC_SP M/S and SAI_SP M/S in register The Left/Right clock (SAI_LRCK or CX_LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS42528 (Master Mode may be generated by an external source (Slave Mode). As described in later sections, particular modes of operation do allow the sample rate, Fs, of the SAI_SP and the CODEC_SP to be different, but must be multiples of each other ...

Page 28

... ADC #2 One-Line Mode ADC channels 1,2,3,4,5,6 S/PDIF Left or ADC #1 left channel right channel S/PDIF Right or ADC #2 One-Line Mode ADC channels 1,2,3,4,5,6 External ADC #3 left channel right channel External ADC #4 left channel External ADC #5 right channel External ADC #6 CS42528 DS586F1 ...

Page 29

... Formats (address 04h)” on page Left Channel + LSB MSB SCLK Rate(s) Slave 48, 64, 128 Fs Single-Speed Mode 64 Fs Double-Speed Mode 64 Fs Quad-Speed Mode 48, 64, 128 Fs Single-Speed Mode 48 Double-Speed Mode 48 Quad-Speed Mode Figure 10. I²S Serial Audio Formats CS42528 Right Channel - LSB Notes 50. 29 ...

Page 30

... Fs Single-Speed Mode 48 Double-Speed Mode 48 Quad-Speed Mode Figure 11. Left-Justified Serial Audio Formats SCLK Rate(s) Slave 32, 48, 64, 128 Fs Single-Speed Mode 32 Double-Speed Mode 32 Quad-Speed Mode 48, 64, 128 Fs Single-Speed Mode 48 Double-Speed Mode 48 Quad-Speed Mode CS42528 Right Channel - LSB Notes Right Channel Notes DS586F1 ...

Page 31

... DAC3 DAC5 DAC2 24 clks 24 clks 24 clks DAC8 24 clks ADC3 ADC5 ADC2 24 clks 24 clks 24 clks SCLK Rate(s) Slave Not supported Single-Speed Mode CS42528 64 clks Right Channel MSB LSB MSB LSB MSB DAC4 DAC6 20 clks 20 clks ADC4 ADC6 20 clks 20 clks Notes 128 clks ...

Page 32

... Figure 15. ADCIN1/ADCIN2 Serial Audio Format For proper operation, the CS42528 must be configured to select which SCLK/LRCK is being used to clock the external ADCs. The EXT ADC SCLK bit in register set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the CODEC_SP clocks. If the ADCs are wired to use the SAI_SP clocks, set this bit to ‘ ...

Page 33

... SPDIF Data RMCK SAI_SDOUT ADCIN1 64Fs,128Fs, 256Fs CX_SCLK ADCIN2 CX_LRCK ADC Data CX_SDOUT CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4 CS42528 Figure 16. OLM Configuration #1 CS42528 Description One-Line Mode #2 not valid not valid CX_SCLK=256 Fs CX_LRCK=SSM SAI_SCLK=64 Fs SAI_LRCK=CX_LRCK MCLK SCLK_PORT1 LRCK_PORT1 SDIN_PORT1 SCLK_PORT2 LRCK_PORT2 SDIN_PORT2 SCLK_PORT3 ...

Page 34

... ADC Data SDIN_PORT1 RMCK SAI_SDOUT ADCIN1 64Fs,128Fs SCLK_PORT2 CX_SCLK ADCIN2 LRCK_PORT2 CX_LRCK SDIN_PORT2 CX_SDOUT SCLK_PORT3 LRCK_PORT3 SDOUT1_PORT3 CX_SDIN1 CX_SDIN2 SDOUT2_PORT3 CX_SDIN3 SDOUT3_PORT3 CX_SDIN4 SDOUT4_PORT3 CS42528 Figure 17. OLM Configuration #2 CS42528 Description One-Line Mode #2 not valid not valid not valid DIGITAL AUDIO PROCESSOR DS586F1 ...

Page 35

... SDIN_PORT1 RMCK SAI_SDOUT ADCIN1 64Fs,128Fs CX_SCLK ADCIN2 CX_LRCK ADC Data CX_SDOUT SDIN_PORT2 CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4 CS42528 Figure 18. OLM Configuration #3 CS42528 Description One-Line Mode #2 not valid not valid not valid MCLK SCLK_PORT1 LRCK_PORT1 SCLK_PORT2 LRCK_PORT2 SCLK_PORT3 LRCK_PORT3 SDOUT1_PORT3 SDOUT2_PORT3 SDOUT3_PORT3 SDOUT4_PORT3 ...

Page 36

... SAI_SCLK SAI_LRCK ADC Data RMCK SAI_SDOUT ADCIN1 64Fs,128Fs,256Fs CX_SCLK ADCIN2 CX_LRCK CX_SDOUT CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4 CS42528 Figure 19. OLM Configuration #4 CS42528 Description One Line Mode #2 CX_SCLK=256 Fs CX_LRCK=SSM SAI_SCLK=64 Fs SAI_LRCK=SSM/DSM/QSM CX_SCLK=256 Fs CX_LRCK=SSM SAI_SCLK=128 Fs SAI_LRCK=SSM not valid MCLK SCLK_PORT1 LRCK_PORT1 SDIN_PORT1 SCLK_PORT2 LRCK_PORT2 ...

Page 37

... SCLK_PORT2 CX_SCLK ADCIN2 LRCK_PORT2 CX_LRCK ADC Data CX_SDOUT SDIN_PORT2 SCLK_PORT3 LRCK_PORT3 SDOUT1_PORT3 CX_SDIN1 CX_SDIN2 SDOUT2_PORT3 CX_SDIN3 SDOUT3_PORT3 CX_SDIN4 SDOUT4_PORT3 DIGITAL AUDIO CS42528 PROCESSOR Figure 20. OLM Configuration #5 CS42528 Description ADC are supported One-Line Mode #2 not valid not valid not valid 37 ...

Page 38

... The control port has two modes: SPI and I²C, with the CS42528 acting as a slave device. SPI mode is se- lected if there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state ...

Page 39

... CS42528 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42528, the chip address field, which is the first byte sent to the CS42528, should match 10011, followed by the settings of the AD1 and AD0 ...

Page 40

... When RST is low, the CS42528 enters a low-power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes opera- tional, and the desired settings should be loaded into the control registers ...

Page 41

... The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42528 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µ ...

Page 42

... AES AES AES Active_CLK RVCR_CLK2 RVCR_CLK1 Format1 Format0 PC0-5 PC0 PC1-5 PC1 PD0-5 PD0 PD1-5 PD1 SZC1 SZC0 AMUTE B3_MUTE A3_MUTE B2_MUTE CS42528 Rev_ID2 Rev_ID1 PDN_DAC2 PDN_DAC1 ADC_SP DAC_DEM RCVR_DEM SEL1 SEL0 DAC_OL0 SAI_RJ16 CODEC_RJ16 HPF_ CODEC_SP FREEZE M SW_CTRL1 SW_CTRL0 FRC_PLL_LK ...

Page 43

... INV_A3 INV_B2 Reserved P1_ATAPI4 P1_ATAPI3 Reserved P2_ATAPI4 P2_ATAPI3 Reserved P3_ATAPI4 P3_ATAPI3 Reserved P4_ATAPI4 P4_ATAPI3 LGAIN5 LGAIN4 LGAIN3 RGAIN5 RGAIN4 RGAIN3 CS42528 A1_VOL2 A1_VOL1 A1_VOL0 B1_VOL2 B1_VOL1 B1_VOL0 A2_VOL2 A2_VOL1 A2_VOL0 B2_VOL2 B2_VOL1 B2_VOL0 A3_VOL2 A3_VOL1 A3_VOL0 B3_VOL2 B3_VOL1 B3_VOL0 A4_VOL2 A4_VOL1 ...

Page 44

... CCRC UNLOCK CCRCM UNLOCKM MCPolarity M_AOUTA1 M_AOUTB1 M_AOUTA2 Polarity Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 Polarity Function4 Function3 CS42528 INT1 INT0 HOLD1 RMUX2 RMUX1 DETU Reserved OverFlow DETUM Reserved OverFlowM DETU1 Reserved OF1 DETU0 Reserved OF0 BSEL CAM ...

Page 45

... X X Second5 Second4 Second3 Frame5 Frame4 Zero6 Zero5 Zero4 A.Minute5 A.Minute4 A.Minute3 A.Second5 A.Second4 A.Second3 A.Frame5 A.Frame4 A.Frame3 Buffer5 CU Buffer4 CU Buffer3 CS42528 Function2 Function1 Function2 Function1 Function2 Function1 Control2 Control1 Track3 Track2 Track1 Index3 Index2 Index1 Minute3 Minute2 Minute1 Second2 Second1 ...

Page 46

... Chip I.D. and Revision Register (address 01h) (Read Only Chip_ID3 Chip_ID2 Chip_ID1 6.2.1 CHIP I.D. (CHIP_IDX) Default = 1111 Function: I.D. code for the CS42528. Permanently set to 1111. 6.2.2 CHIP REVISION (REV_IDX) Default = xxxx Function: CS42528 revision level. Revision D is coded as 0100. Revision C is coded as 0011 ...

Page 47

... The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur. DS586F1 PDN_DAC4 PDN_DAC3 CS42528 PDN_DAC2 PDN_DAC1 PDN 47 ...

Page 48

... De-emphasis will not be enabled, regardless of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the SAI_FM0 ADC_SP SEL1 ADC_SP SEL0 CS42528 DAC_DEM RCVR_DEM DS586F1 ...

Page 49

... RCVR_DEM reg03h[ DS586F1 FRC_PLL_LK DE-EMPH[1:0] reg06h[0] reg1Eh[5: Table 5. DAC De-Emphasis FRC_PLL_LK DE-EMPH[1:0] reg06h[0] reg1Eh[5: Table 6. Receiver De-Emphasis CS42528 De-Emphasis Mode No De-Emphasis Auto-Detect Fs Reserved 32 kHz 44.1 kHz 48 kHz De-Emphasis Mode No De-Emphasis Auto-Detect Fs Reserved 32 kHz 44.1 kHz 48 kHz 49 ...

Page 50

... Description DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2 Reserved Table 8. ADC One-Line Mode 13 and 14 Description DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2 Reserved Table 9. DAC One-Line Mode CS42528 2 1 DAC_OL0 SAI_RJ16 CODEC_RJ16 Format Figure see the format of One-Line Mode 1 and ...

Page 51

... One-Line Mode of operation SAI_SCLK is used as external ADC SCLK CX_SCLK is used as external ADC SCLK. 6.6.2 RMCK HIGH IMPEDANCE (HIZ_RMCK) Default = 0 Function: This bit is used to create a high-impedance output on RMCK when the clock signal is not required. DS586F1 FREEZE FILT_SEL CS42528 2 1 HPF_FREEZE CODEC_SP SAI_SP M/S M ...

Page 52

... In Master Mode, SAI_SCLK and SAI_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave Mode, SAI_SCLK and SAI_LRCK become inputs. If the SAI_SP is in Slave Mode, SAI_LRCK must be present for proper device operation. 52 “D/A Digital Filter Characteristics” on page 9. CS42528 11. “A/D Dig- DS586F1 ...

Page 53

... PLL LOCK TO LRCK (PLL_LRCK) Default = Disabled 1 - Enabled Function: When enabled, the internal PLL of the CS42528 will lock to the SAI_LRCK of the SAI serial port. 6.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX) Default = 00 Function: These two bits, along with the UNLOCK bit in register on page 63, determine the master clock source for the CS42528 ...

Page 54

... DIGITAL SILENCE DETECTION (DIGITAL SILENCE) Default = Digital Silence not detected 1 - Digital Silence detected Function: The CS42528 will auto-detect a digital silence condition when 1548 consecutive zeros have been de- tected Manual setting, MCLK sourced from PLL. X Manual setting, MCLK sourced from OMCK. ...

Page 55

... RECEIVER CLOCK FREQUENCY (RCVR_CLKX) Default = xxx Function: The CS42528 detects the ratio between the OMCK and the recovered clock from the PLL. Given the absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL clock 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX ...

Page 56

... Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will PCx-4 PCx-3 PDx-4 PDx SZC0 AMUTE CS42528 Description 8.1920 MHz 11.2896 MHz 12.288 MHz 16.3840 MHz 22.5792 MHz 24.5760 MHz 45.1584 MHz 49.1520 MHz 2 1 PCx-2 PCx-1 PCx-0 PDx-2 PDx-1 PDx MUTE SAI_SP RAMP_UP RAMP_DN DS586F1 0 0 ...

Page 57

... Enabled Function: The digital-to-analog converters of the CS42528 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the MUTEC pin will go active during the mute period ...

Page 58

... Default = Disabled 1 - Enabled Function: The digital-to-analog converter outputs of the CS42528 will mute when enabled. The quiescent volt- age on the outputs will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). 6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ...

Page 59

... Volume Control registers when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Volume Control registers (per A-B pair), and the B Channel Volume Control registers are ignored when this function is enabled. DS586F1 INV_A3 INV_B2 Px_ATAPI4 Px_ATAPI3 CS42528 INV_A2 INV_B1 INV_A1 Px_ATAPI2 Px_ATAPI1 Px_ATAPI0 59 ...

Page 60

... ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42528 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 Table 16 ATAPI1 ATAPI0 AOUTAx MUTE MUTE MUTE MUTE a[(L+R)/ a[(L+R)/2] ...

Page 61

... DS586F1 LGAIN4 LGAIN3 RGAIN4 RGAIN3 Decimal Value +15 + -10 -15 Table 17. Example ADC Input Gain Settings DE-EMPH0 INT1 CS42528 2 1 LGAIN2 LGAIN1 LGAIN0 2 1 RGAIN2 RGAIN1 RGAIN0 Volume Setting + - INT0 HOLD1 HOLD0 ...

Page 62

... AUDIO SAMPLE HOLD (HOLDX) Default = Hold the last valid audio sample 01 - Replace the current audio sample with 00 (mute not change the received audio sample 11 - Reserved Function: Determines how received audio samples are affected when a receiver error occurs. 62 CS42528 “Force PLL Lock (FRC_PLL_LK)” on DS586F1 ...

Page 63

... Input from pin RXP3 0 0 Input from pin RXP4 0 1 Input from pin RXP5 1 0 Input from pin RXP6 1 1 Input from pin RXP7 Table 19. Receiver Input Selection DETC DETU CS42528 2 1 RMUX2 RMUX1 RMUX0 Description Description 2 1 Reserved OverFlow RERR ...

Page 64

... Function: Indicates when the user status buffer has changed. 6.20.5 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42528 ADC signal path. 6.20.6 RECEIVER ERROR (RERR) Default = 0 Function: Indicates that a receiver error has occurred. The register on page 67 may be read to determine the nature of the error which caused the interrupt ...

Page 65

... Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data Function: Selects the data buffer register addresses to contain either User data or Channel Status data. DS586F1 DETC1 DETU1 DETC0 DETU0 61 Reserved Reserved CS42528 Reserved OF1 RERR1 Reserved OF0 RERR0 “Receiver Mode BSEL CAM CHS 65 ...

Page 66

... Auxiliary data is 4 bit long 0 1 Auxiliary data is 5 bit long 1 0 Auxiliary data is 6 bit long 1 1 Auxiliary data is 7 bit long 0 0 Auxiliary data is 8 bit long 0 1 1001 - 1111 is Reserved Table 20. Auxiliary Data Width Selection CS42528 AUDIO COPY ORIG DS586F1 ...

Page 67

... Function: Indicates a Q-subcode data CRC error. This bit is updated on Q-subcode block boundaries. 6.25.2 REDUNDANCY CHECK (CCRC) Default = error 1 - Error Function: Indicates a channel status block cyclic redundancy. This bit is updated on CS block boundaries, valid in Professional mode. DS586F1 UNLOCK V CS42528 CONF BIP PAR 67 ...

Page 68

... The bits in this register serve as masks for the corresponding bits of the Receiver Errors register mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver errors register, will affect the RERR interrupt, and will affect the current audio sample according UNLOCKM VM CS42528 CONFM BIPM PARM DS586F1 ...

Page 69

... Mute Mode - The pin is configured as a dedicated mute pin. The muting function is controlled by the Function bits. GPO, Drive Low / ADC Overflow Mode - The pin is configured as a general-purpose output driven low DS586F1 M_AOUTA1 M_AOUTB1 Function4 Function3 CS42528 M_AOUTA2 M_AOUTA3 M_AOUTA4 M_AOUTB2 M_AOUTB3 M_AOUTB4 Function2 ...

Page 70

... M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTB3 M_AOUTA1 M_AOUTA2 M_AOUTA3 M_AOUTB1 M_AOUTB2 M_AOUTB3 CS42528 Function1 Function0 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA3 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA4 M_AOUTB3 M_AOUTB4 M_AOUTA4 M_AOUTB3 M_AOUTB4 ...

Page 71

... Track3 Index4 Index3 Minute4 Minute3 Second4 Second3 Frame4 Frame3 Zero4 Zero3 A.Minute4 A.Minute3 A.Second4 A.Second3 A.Frame4 A.Frame3 Buffer4 CU Buffer3 CS42528 Driver Type CMOS Open Drain Control2 Control1 Control0 Track2 Track1 Track0 Index2 Index1 Index0 Minute2 Minute1 Minute0 Second2 Second1 Second0 Frame2 ...

Page 72

... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 72 CS42528 DS586F1 ...

Page 73

... DAC Output Filter The CS42528 is a linear phase design and does not include phase or amplitude compensation for an exter- nal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external an- alog circuitry. AOUT - AOUT + Figure 25. Recommended Analog Output Buffer DS586F1 Ω ...

Page 74

... Audio data routed to the Serial Audio Interface port is unaffected by the word length settings; all 24 bits are passed on as received. The CS42528 also contains sufficient RAM to store a full block of C data for both A and B channels (192 384 bits), and also 384 bits of User (U data) information. The user may read from these buffer RAMs through the control port ...

Page 75

... In these situations, Two-Byte Mode should be used to access the E buffer. In this mode, a read will cause the CS42528 to output two bytes from its control port. The first byte out will represent the A channel status data, and the second byte will represent the B channel status data. ...

Page 76

... Channel Status section. The user has access to the E buffer through the control port Data Buffer which is mapped into the register space of the CS42528. The Data Buffer must first be configured to point to the address space of the U data. This is accomplished by setting the BSEL bit to ‘1’ in the register “ ...

Page 77

... PLL component 0.047 2200 00 0.047 2200 01 0.022 1000 10 CS42528 RM CK VCO Notes Used for backward compatibility with Revision C devices. Default configuration for Revision D devices. Provides improved wideband jitter rejection in Double- and Quad-Speed modes. Provides improved in-band jitter rejection, with increased wideband jitter ...

Page 78

... CS42528 Revision C. Using the Revision D default locking mode of ‘01’ will provide improved wide- band jitter rejection in Double- and Quad-Speed modes. Configuration 3 may be used for new designs with the CS42528 Revision D, or for existing designs in which the hardware and software may be changed to use the specified PLL component values and LOCKM[1:0] register setting ...

Page 79

... The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to the SAI_LRCK input. These specifications state a maximum jitter gain or peaking. Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3 DS586F1 CS42528 Table 21. 79 ...

Page 80

... The traces themselves are short to minimize the inductance in the filter path. The VARX and AGND traces extend back to their origin and are shown only in truncated form in the drawing. 80 0.01 µF CRIP 0.1 µF CFILT 10 µF = via to ground plane Figure 30. Recommended Layout Example CS42528 DS586F1 ...

Page 81

... D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS 11.1 AES3 Receiver External Components The CS42528 AES3 receiver is designed to accept only consumer-standard interfaces. The standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector is an RCA phono socket. The receiver circuit is shown in plexer using the consumer interface ...

Page 82

... Figure 39. Double-Speed Mode Transition Band CS42528 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Frequency (normalized to Fs) 0.48 ...

Page 83

... Figure 45. Quad-Speed Mode Passband Ripple CS42528 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 Frequency (normalized to Fs) 0 ...

Page 84

... Figure 49. Single-Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 51. Single-Speed (slow) Transition Band CS42528 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) ...

Page 85

... Figure 55. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 57. Double-Speed (fast) Passband Ripple CS42528 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...

Page 86

... Figure 61. Double-Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 63. Quad-Speed (fast) Transition Band CS42528 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...

Page 87

... Figure 67. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 69. Quad-Speed (slow) Passband Ripple CS42528 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...

Page 88

... BSC 0.484 0.393 BSC 0.398 0.472 BSC 0.484 0.393 BSC 0.398 0.020 BSC 0.024 0.024 0.030 4° 7.000° Symbol θ CS42528 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.20 0.27 11.70 12.0 BSC 12 ...

Page 89

... Philips Semiconductor, The I2C-Bus Specification: Version 2.1, January 2000. ductors.philips.com DS586F1 Package Pb-Free Grade Commercial -10° to +70° C 64-pin YES LQFP Automotive -40° to +85° CS42528 Temp Range Container Order # CS42528-CQZ Tray Tape & Reel CS42528-CQZR Tray CS42528-DQZ Tape & Reel CS42528-DQZR CDB42528 - - http://www.semicon- 89 ...

Page 90

... Updated “Slave Mode” section on – Updated specification and t dpd on page 12. – Updated the “External Filter Components” section beginning on – Updated LOCKM[1:0] bits and description on – Updated RCVR_CLK[2:0] bit description on CS42528 on page 53. 77. page 47. page 65. page 8. page in the Switching Characteristics table on dh ...

Page 91

... AC registered trademark of Dolby Laboratories, Inc. DTS is a registered trademark of Digital Theater Systems, Inc. HDCD is a registered trademark of Microsoft Corporation. HDCD technology cannot be used or distributed without a license from Microsoft Licensing, Inc. SPI is a trademark of Motorola, Inc. DS586F1 www.cirrus.com/corporate/contacts/sales.cfm CS42528 91 ...

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