W6810ISG Nuvoton Technology Corporation of America, W6810ISG Datasheet - Page 11

• Manufacturer Part Number: W6810ISG
• Description: IC VOICEBAND CODEC 5V 1CH 20SOP
• Manufacturer: Nuvoton Technology Corporation of America
• Type: PCMr

Specifications of W6810ISG

• Data Interface: PCM Audio Interface
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: W6810ES - EVALUATION SYSTEM FOR W6810W6810DK - KIT DEV/EVAL FOR W6810
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

7.3. Power Management
The power supply for the analog and digital parts of the W6810 must be 5V +/- 10%. This supply
voltage is connected to the V
ceramic capacitor.
The system has an internal precision voltage reference which generates the 2.5V mid-supply analog
ground voltage. This voltage needs to be decoupled to V
capacitor.
The analog ground reference voltage is available for external reference at the V
needs to be decoupled to V
voltage is generated from the voltage on the V
processing.
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8
kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC
sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when
the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The
length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge
occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin
PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data
7.4 PCM I
7.3.1. Analog and Digital Supply
7.3.2. Analog Ground Reference Bypass
7.3.3. Analog Ground Reference Voltage Outpt
7.4.1. Long Frame Sync
NTERFACE
BCLKR (Pin 9)
64 kHz to 4.096 MHz
V
V
V
V
SS
SS
DD
DD
SS
DD
through a 0.01 μF ceramic capacitor. The analog ground reference
Table 7.3 PCM Interface mode selections
pin. The V
8 kHz
FSR (Pin 7)
V
V
V
V
SS
DD
SS
DD
DD
pin needs to be decoupled to ground through a 0.1 μF
- 11 -
REF
Interface Mode
Long or Short Frame Sync
ISDN GCI with active channel B1
ISDN GCI with active channel B2
ISDN IDL with active channel B1
ISDN IDL with active channel B2
pin and is also used for the internal signal
SS
at the V
Publication Release Date: January 2009
REF
pin through a 0.1 μF ceramic
AG
pin. This voltage
W6810
Revision A14