LM4546BVH/NOPB National Semiconductor, LM4546BVH/NOPB Datasheet - Page 22

• Manufacturer Part Number: LM4546BVH/NOPB
• Description: IC AUDIO CODEC 2MULTICH 48-LQFP
• Manufacturer: National Semiconductor
• Type: Audio Codec '97r

Specifications of LM4546BVH/NOPB

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 89
• Voltage - Supply, Analog: 4.2 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM4546BVH

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Register Descriptions
RECORD GAIN REGISTER (1Ch)
This register controls the input levels for both channels of the
stereo ADC. The inputs come from the Record Select Mux
and are selected via the Record Select Control register, 1Ah.
The gain of each channel can be individually programmed
from 0 dB to +22.5 dB in 1.5 dB steps. Both channels can
also be muted by setting the MSB to 1.
GENERAL PURPOSE REGISTER (20h)
This register controls many miscellaneous functions imple-
mented on the LM4546B. The miscellaneous control bits
include POP which allows the DAC output to bypass the
National 3D Sound circuitry, 3D which enables or disables
the National 3D Sound circuitry, MIX which selects the MO-
NO_OUT source, MS which controls the Microphone Selec-
tion mux, and LPBK which connects the 18 bit output of the
stereo ADC to the 18 bit input of the stereo DAC, bypassing
the Sample Rate Conversion (SRC) logic. LPBK provides a
mixed-mode analog and digital loopback path between ana-
log inputs and analog outputs.
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with
the AC ’97 Rev 2.1 Specification, the fixed depth and center
characteristics of the National 3D Sound stereo enhance-
ment.
POWERDOWN CONTROL / STATUS REGISTER (26h)
This read/write register is used both to monitor subsystem
readiness and also to program the LM4546B powerdown
states. The 4 LSBs indicate status and 6 of the 8 MSBs
control powerdown.
The 4 LSBs of this register indicate the status of the 4 audio
subsections of the codec: Reference voltage, Analog mixers
and amplifiers, DAC section, ADC section. When the "Codec
Ready" indicator bit in the AC Link Input Frame (SDATA_IN:
slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97
registers are in a fully operational state and that control and
Default: 8000h
Default: 0000h
LPBK
Mute
POP
MIX
BIT
MS
3D
0
0
1
PCM Out Path:
National 3D Sound:
Mono output select:
Mic select:
ADC/DAC Loopback: *0 = No Loopback
Record Gain Register (1Ch)
Gx3:Gx0
XXXX
0000
1111
+22.5 dB gain
0 dB gain
*mute
Function
*0 = 3D allowed
*0 = off
*0 = Mix
*0 = MIC1
1 = 3D bypassed
1 = on
1 = Mic
1 = MIC2
1 = Loopback
(Continued)
Function
22
status information can be transferred. It does NOT indicate
that the codec is ready to send or receive audio PCM data or
to pass signals through the analog I/O and mixers. To deter-
mine that readiness, the Controller must check that the 4
LSBs of this register are set to “1” indicating that the appro-
priate audio subsections are ready.
The powerdown bits PR0 – PR5 control internal subsections
of the codec. They are implemented in compliance with AC
’97 Rev 2.1 to support the standard device power manage-
ment states D0 – D3 as defined in the ACPI and PCI Bus
Power Management specification.
PR0 controls the powerdown state of the ADC and associ-
ated sampling rate conversion circuitry. PR1 controls power-
down for the DAC and the DAC sampling rate conversion
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,
National 3D Sound, Mono Out, Line Out). PR3 powers down
V
powers down the AC Link digital interface – see Figure 8 for
signal powerdown timing. PR5 disables internal clocks. PR6
and PR7 are not used.
EXTENDED AUDIO ID REGISTER (28h)
This read-only register (X001h) identifies which AC ’97 Ex-
tended Audio features are supported. The LM4546B features
VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec
support). VRA is indicated by a "1" in bit 0. The two MSBs,
ID1 and ID0, show the current Codec Identity as defined by
the Identity pins ID1#, ID0# (pins 46 and 45). Note that the
external logic connections to ID1#, ID0#, are inverse in
polarity to the value of the Codec Identity (ID1, ID0) held in
bits D15, D14. Codec mode selections are shown in the
table below.
NC/DV
NC/DV
REF
Default: 000Fh If ready; otherwise 000Xh (see text)
Pin 46
(ID1)
BIT#
BIT#
10
11
12
13
14
15
in addition to all the same mixer circuits as PR2. PR4
0
1
2
3
8
9
DD
DD
NC/DV
Pin 45
(ID0)
GND
ADC
DAC
REF
ANL
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
BIT
BIT
DD
D15,28h
Not Used
Not Used
(ID1)
1 = ADC section ready to
1 = DAC section ready to
1 = Analog mixers ready
1 = V
1 = Powerdown ADCs and
1 = Powerdown DACs
1 = Powerdown Analog Mixer
1 = Powerdown Analog Mixer
1 = Powerdown AC Link digital
1 = Disable Internal Clock
0
0
Function: Powerdown
transmit data
accept data
Record Select Mux
(V
(V
interface (BIT_CLK off)
REF
Function: Status
REF
REF
D14,28h
(ID0)
is up to nominal level
0
1
still on)
off)
Codec Identity
Primary
Secondary 1
Mode