STW5093CYL ST-Ericsson Inc, STW5093CYL Datasheet - Page 6

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STW5093CYL

Manufacturer Part Number
STW5093CYL
Description
IC FILTR/CODEC 14BIT AUD 30TSSOP
Manufacturer
ST-Ericsson Inc
Type
Stereo Audior
Datasheet

Specifications of STW5093CYL

Data Interface
PCM Audio Interface
Resolution (bits)
14 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
No
Voltage - Supply, Analog
2.7 V ~ 3.3 V
Voltage - Supply, Digital
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
30-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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STw5093
mit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de-
layed reverse mode.A separate MBIAS output can be used to bias a microphone (bit MB = 1 in register CR10)
1.1.5 Receive section:
Voice Data is shifted into the decoder's Receive voice data Register via the DR pin during the selected time slot
on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in non-
delayed reverse mode.
The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decoding characteristic.
Following the Decoder is a 3400 Hz 8th order band-pass switched capacitor filter with integral Sin X/X correction
for the 8 kHz sample and hold.
0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A transcient suppress-
ing circuitry ensure interference noise suppression at power up.
The analog speech signal output can be routedeither to earpiece (VFR output) or to an extra analog output (V
V
Total signal delay is approximatively 190µs (filter plus decoding delay) plus 62.5µs (1/2 frame) which gives ap-
proximatively 252µs.
Output VFR is intended to directly drive an earpiece. Preceding the outputs is a programmable attenuation am-
plifier, which must be set by writing to bits 4 to 7 in register CR6. Attenuations in the range 0 to -30 dB relative
to the maximum level in 2 dB step can be programmed. The input of this programmable amplifier is the sum of
several signals which can be selected by writing to register CR4.:
V
between V
Differential outputs V
mable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range
0 to -30 dB relative to the maximum level in 2.0 dB step can be programmed. The input of this programmable
amplifier can be the sum of signals which can be selected by writing to register CR4:
V
impedance of 8 Ω. Piezoceramic receivers up to 50nF can also be driven.
BUZZER OUTPUT:
Single ended output BZ is intended to drive a buzzer, via an external BJT, with a squarewave pulse width mod-
ulated (PWM) signal the frequency of which is stored into register CR8.
For some applications it is also possible to amplitude modulate this PWM signal with a squarewave signal hav-
ing a frequency stored in register CR9.
Maximum load for BZ is 5kΩ and 50pF.
1.1.6 Digital Interface (Fig. 1)
F
to a squarewave. Three different relationships may be established between the Frame Sync input and the first
time slot of frame by setting bits DM1 and DM0 in register CR1. In non delayed data mode (long frame timing)
the first time slot begins nominally coincident with the rising edge of F
(short frame sync timing) in which FS input must be high at least a half cycle of MCLK earlier the frame beginning
In the case of linear code (bit CM = 0 in register CR0) the MSB is the first bit that is transmitted and received.
6/34
S
Lr-
Fr
Lr+
Frame Sync input determines the beginning of frame. It may have any duration from a single cycle of MCLK
is capable of driving output power levels up to 16.5mW into a 30Ω load impedance capacitively connected
outputs) by setting bits OE1, OE2, and SE (4, 3, and 0 of CR4).
and V
- Receive speech signal which has been decoded and filtered,
- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7),
- Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5
- Receive speech signal which has been decoded and filtered,
- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7),
- Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5.
Fr+
Lr-
outputs are capable of driving output power level up to140mW into differentially connected load
and GND. Piezoceramic receivers up to 50nF can also be driven.
Lr+
,V
Lr-
are intended to directly drive an extra output. Preceding the outputs is a program-
S
. Alternative is to use delayed data mode
Lr+
,

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