ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 101

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
Table 88.
Table 90.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 0
Symbol
PTDDoneBits[31:0] R
HcINTLBlkSize register: bit allocation
HcINTLPTDDoneMap register: bit description
14.8.3 HcINTLBlkSize register (R/W: 53h/D3h)
14.8.4 HcINTLPTDDoneMap register (R: 17h)
14.8.5 HcINTLPTDSkipMap register (R/W: 18h/98h)
R/W
15
7
0
-
-
The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so
that the Host Controller can skip the current PTD and proceed to process the next PTD
easily. The block size of the INTL buffer is required to be specified in this register and must
be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the maximum
allowable block size is 1024 bytes.
Code (Hex): 53 — read
Code (Hex): D3 — write
Table 89.
This is a 32-bit register, and the bit description is given in
register represents the processing status of a PTD. Bit 0 of the register represents the first
PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so
on. The register is updated once every ms by the Host Controller and is cleared on read
by the HCD. Bits that are set represent its corresponding PTDs are processed by the Host
Controller and the ACK token is received from the device.
Code (Hex): 17 — read only
This is a 32-bit register, and the bit description is given in
represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. When a bit is set by the HCD, the corresponding PTD is skipped
and is not processed by the Host Controller. The Host Controller processes the skipped
Bit
15 to 10
9 to 0
Access
R/W
14
6
0
-
-
HcINTLBlkSize register: bit description
Symbol
-
BlockSize[9:0]
Value
0000h
R/W
13
5
0
-
-
reserved
Rev. 05 — 8 May 2007
Description
0 — The PTD stored in the INTL buffer has not successfully been
processed by the Host Controller.
1 — The PTD stored in the INTL buffer has successfully been
processed by the Host Controller.
Description
reserved
The block size of the INTL buffer.
R/W
12
4
0
-
-
BlockSize[7:0]
Table 88
R/W
shows the bit allocation of the register.
11
3
0
-
-
Single-chip USB OTG Controller
R/W
10
2
0
Table
Table
-
-
90. Every bit of the
91. Bit 0 of the register
R/W
R/W
9
0
1
0
BlockSize[9:8]
© NXP B.V. 2007. All rights reserved.
ISP1362
100 of 152
R/W
R/W
8
0
0
0