ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 114

IC USB OTG CONTROLLER 64-LQFP

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362BDFA

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDFA
Manufacturer:
STE
Quantity:
5
Part Number:
ISP1362BDFA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 119. DcDMAConfiguration register: bit allocation
[1]
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
15.1.6 DcDMAConfiguration (R/W: F1h/F0h)
CNTREN
R/W
R/W
0
0
15
7
[1]
[1]
Table 118. DcInterruptEnable register: bit description
This command defines the DMA configuration of the Peripheral Controller, and enables or
disables DMA transfers. The command accesses the DcDMAConfiguration register, which
consists of two bytes. The bit allocation is given in
bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write or read DMA Configuration
Transaction — write or read 2 bytes (code or data)
Table 120. DcDMAConfiguration register: bit description
Bit
2
1
0
Bit
15
14
13 to 8 -
7 to 4
SHORTP
R/W
R/W
0
0
14
6
[1]
[1]
Symbol
CNTREN
SHORTP
EPDIX[3:0]
EPDIX[3:0]
Symbol
IESUSP
IERESM
IERST
R/W
0
13
5
-
-
[1]
Description
Logic 1 enables the generation of an EOT condition, when the
DcDMACounter register reaches zero. Bus reset value: unchanged.
Logic 1 enables short or empty packet mode. When receiving (OUT
endpoint) a short or empty packet, an EOT condition is generated. When
transmitting (IN endpoint), this bit must be cleared. Bus reset value:
unchanged.
reserved
Indicates the destination endpoint for DMA, see
Rev. 05 — 8 May 2007
Description
Logic 1 enables interrupt on detecting a suspend state. Logic 0
disables interrupt.
Logic 1 enables interrupt on detecting a resume state. Logic 0
disables interrupt.
Logic 1 enables interrupt on detecting a bus reset. Logic 0 disables
interrupt.
R/W
0
12
4
-
-
[1]
DMAEN
R/W
11
3
0
-
-
reserved
Table
…continued
reserved
Single-chip USB OTG Controller
119. A bus reset will clear
10
2
-
-
-
-
Table
R/W
0
9
1
-
-
[1]
BURSTL[1:0]
© NXP B.V. 2007. All rights reserved.
17.
ISP1362
113 of 152
R/W
0
8
0
-
-
[1]

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