ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 117

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
Table 125. DcEndpointStatus register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
15.2.2 Read endpoint status (R: 50h to 5Fh)
EPSTAL
R
7
0
Table 124. Example of endpoint buffer memory access
Remark: There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions can
cause an incorrect operation. Data residing in an OUT buffer is only meaningful after a
successful transaction. Exception: during the DMA access of a double-buffered endpoint,
the buffer pointer automatically points to the secondary buffer after reaching the end of the
primary buffer.
This command is used to read the status of an endpoint buffer memory. The command
accesses the DcEndpointStatus register, the bit allocation of which is shown in
Reading the DcEndpointStatus register will clear the interrupt bit set for the corresponding
endpoint in the DcInterrupt register (see
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by the
Stall or Unstall commands and by the reception of a set-up token (see
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoints 1 to 14)
Transaction — read 1 byte (code only)
Table 126. DcEndpointStatus register: bit description
A0
HIGH
LOW
LOW
LOW
…
Bit
7
6
5
4
EPFULL1
R
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
6
0
Phase
command
data
data
data
…
EPFULL0
R
5
0
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =
not stalled).
Set to logic 1 by a stall endpoint command, cleared to logic 0 by an
Unstall Endpoint command. The endpoint is automatically unstalled on
receiving a set-up token.
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates data PID of the next packet (0 = DATA PID; 1 = DATA1
PID).
Rev. 05 — 8 May 2007
Bus lines
D[7:0]
D[15:8]
D[15:0]
D[15:0]
D[15:0]
…
DATA_PID
R
4
0
Word #
-
-
0
1
2
…
Table
WRITE
OVER
R
3
0
141).
Description
command code (00h to 1Fh)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
…
SETUPT
Single-chip USB OTG Controller
R
2
0
CPUBUF
R
1
0
Section
© NXP B.V. 2007. All rights reserved.
ISP1362
Table
15.2.3).
reserved
116 of 152
0
-
-
125.