ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 29

IC USB OTG CONTROLLER 64-LQFP

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362BDFA

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S

Available stocks

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ISP1362BDFA
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Manufacturer:
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NXP Semiconductors
ISP1362_5
Product data sheet
8.7.2 Interrupt in the Peripheral Controller
Interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the
HcInterruptStatus register). When any of these events occurs, the corresponding bit will
be set to logic 1, and if the corresponding bit in the HcInterruptEnable register is also
logic 1, the 6-input OR gate will output logic 1. This output is combined with the value of
MIE (bit 31 of HcInterruptEnable) using the AND operation and logic 1 output at this AND
gate will cause the OPR bit in the Hc PInterrupt register to be set to logic 1.
Interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in the
OtgInterrupt register). When any of these events occurs, the corresponding bit will be set
to logic 1, and if the corresponding bit in the OtgInterruptEnable register is also logic 1,
the 11-input OR gate will output logic 1 and cause the OTG_IRQ bit in the Hc PInterrupt
register to be set to logic 1.
Level 1 interrupts contains 10 possible interrupt events. The Hc PInterrupt and
Hc PInterruptEnable registers work in the same way as the HcInterruptStatus and
HcInterruptEnable registers. The output from the 10-input OR gate is connected to a latch,
which is controlled by InterruptPinEnable (the bit 0 of HcHardwareConfiguration register).
When the software wishes to temporarily disable the interrupt output of the ISP1362 Host
Controller and OTG Controller, follow this procedure:
To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1.
Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register controls the
latch of the interrupt output. When this bit is set to logic 0, the interrupt output will remain
unchanged, regardless of any operation on interrupt control registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal without
clearing the Hc PInterrupt register, follow this procedure:
To re-enable the interrupt generation:
The registers that control the interrupt generation in the ISP1362 Peripheral Controller
are:
1. Set the InterruptPinEnable bit in the HcHardwareConfiguration register to logic 1.
2. Clear all bits in the Hc PInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
1. Make sure that the InterruptPinEnable bit is set to logic 1.
2. Clear all bits in the Hc PInterruptEnable register.
3. Set the InterruptPinEnable bit to logic 0.
1. Set all bits in the Hc PInterruptEnable register, according to the HCD requirements.
2. Set the InterruptPinEnable bit to logic 1.
DcMode (bit 3)
DcHardwareConfiguration (bits 0 and 1)
DcInterruptEnable
DcInterrupt
Rev. 05 — 8 May 2007
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
ISP1362
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