ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 50

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
12. USB Peripheral Controller
ISP1362_5
Product data sheet
11.8.4 Overcurrent detection circuit using external 5 V power source in OTG mode
11.9 ISP1362 Host Controller power management
In OTG mode using external 5 V power source for V
the same as that for non-OTG mode (see
In the ISP1362, the Host Controller and the Peripheral Controller are suspended and
woken up individually. The H_SUSPEND/H_WAKEUP and D_SUSPEND/D_WAKEUP
pins must be pulled-up by a large resistor (100 k ). In the suspend state, these pins are
HIGH. To wake up the Host Controller, these pins must be pulled LOW.
The ISP1362 can partially be suspended (only the Host Controller or only the Peripheral
Controller). In the partially suspended state, the clock circuit and PLL continue to work. To
save power, both the Host Controller and the Peripheral Controller must be set to suspend
mode.
The Host Controller can be suspended by writing 06C0h to the HcControl register.
The Host Controller can be set awake by one of the following ways:
On waking up from the suspend state, the clock to the Host Controller will sustain for
5 ms. Within this 5 ms, the HCD must set the Host Controller to operational mode by
writing 0680h to the HcControl register. If the HcControl register remains in the suspend
state (06C0h) after waking up the Host Controller, the Host Controller will return to the
suspend state after 5 ms.
The design of the Peripheral Controller in the ISP1362 is compatible with the NXP
ISP1181B USB full-speed interface device IC. The functionality of the Peripheral
Controller in the ISP1362 is similar to the ISP1181B in 16-bit bus mode. In addition, the
command and register sets are also the same.
In general, the Peripheral Controller in the ISP1362 provides 16 endpoints for the USB
device implementation. Each endpoint can be allocated RAM space in the on-chip ping
pong buffer RAM.
Remark: The ping pong buffer RAM for the Peripheral Controller is independent of the
buffer RAM for the Host Controller. When the buffer RAM is full, the Peripheral Controller
transfers the data in the buffer RAM to the USB bus. When the buffer RAM is empty, an
interrupt is generated to notify the microprocessor to feed in data. The transfer of data
between a microprocessor and the Peripheral Controller can be done in either
Programmed I/O (PIO) mode or in Direct Memory Access (DMA) mode.
•
•
•
A LOW pulse on the H_SUSPEND/H_WAKEUP pin, minimum length of pulse is
25 ns.
A LOW pulse on the chip select (CS) pin, minimum length of pulse is 25 ns.
A resume signal by USB devices connected to the downstream port.
Rev. 05 — 8 May 2007
Section 11.8.1
BUS
Single-chip USB OTG Controller
, the circuit and the operation are
and
Section
11.8.2).
© NXP B.V. 2007. All rights reserved.
ISP1362
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